From patchwork Thu May 3 14:43:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 908068 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-477176-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="h7e9NndS"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40cHvN0P8Tz9s4t for ; Fri, 4 May 2018 00:43:27 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=bol9c6VcIgVNnQPr35ZHTQD//kLCZLI1V34oNJKS5tKcgTSlFU OuZ6n7Q8SN262Gr4IvT1aQbHK3YnumIpXZwRcgq2BC9SFUVRPUIcjxU4p6BgKpPY iSefwS4alrPxSJlR6qMWFjW/n8cgEKQpWx/MR9wXYEVMYzEXngiWNZ97k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=XTwEPr9S0FFQuz9AVHhDqW2iti0=; b=h7e9NndSavjNM2AA7vox I1CdpjeZvDrVJSVju1xdwGNLRCWw5e74cSHQsOWSV4LeF7rZML9fo0tLu1yqxRdj 6k9CvYIug9W8uX3wK25C0L2yy5lmGYcBqVFkLmMpFcn08sqRvFvM0pIRf5BCaIPK vyJS9THXscbzY/zhbFf1jMc= Received: (qmail 44330 invoked by alias); 3 May 2018 14:43:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 43415 invoked by uid 89); 3 May 2018 14:43:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=H*u:38.0, H*UA:38.0, mabi, ilp32 X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 03 May 2018 14:43:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EBAF51435 for ; Thu, 3 May 2018 07:43:15 -0700 (PDT) Received: from [10.2.206.23] (e107157-lin.cambridge.arm.com [10.2.206.23]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9AF533F25D for ; Thu, 3 May 2018 07:43:15 -0700 (PDT) To: GCC Patches From: "Andre Vieira (lists)" Subject: [Aarch64] PR target/83009: Relax strict address checking for store pair lanes Message-ID: <5AEB2002.3090905@arm.com> Date: Thu, 3 May 2018 15:43:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi, See below a patch to address PR 83009. Tested with aarch64-linux-gnu bootstrap and regtests for c, c++ and fortran. Ran the adjusted testcase for -mabi=ilp32. Is this OK for gcc-9? Cheers, Andre PR target/83009: Relax strict address checking for store pair lanes The operand constraint for the memory address of store/load pair lanes was enforcing strictly hardware registers be allowed as memory addresses. We want to relax that such that these patterns can be used by combine. During register allocation the register constraint will enforce the correct register is chosen. gcc 2018-05-xx Andre Vieira PR target/83009 * config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make address check not strict. gcc/testsuite 2018-05-xx Andre Vieira PR target/83009 * gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests. diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 5d41d4350402b2a9e5941f160c6ab6f933bfff90..f29bc8e74f0070589014ac87fd22a95723ba9be8 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -222,7 +222,7 @@ ;; as a 128-bit vec_concat. (define_predicate "aarch64_mem_pair_lanes_operand" (and (match_code "mem") - (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1, + (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 0, ADDR_QUERY_LDP_STP)"))) (define_predicate "aarch64_prefetch_operand" diff --git a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c index 990aea32de6f8239effa95a081950684c6e11386..3296d04da14149d26d19da785663b87bd5ad8994 100644 --- a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c +++ b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c @@ -22,10 +22,32 @@ construct_lane_2 (long long *y, v2di *z) z[2] = x; } +void +construct_lane_3 (double **py, v2df **pz) +{ + double *y = *py; + v2df *z = *pz; + double y0 = y[0] + 1; + double y1 = y[1] + 2; + v2df x = {y0, y1}; + z[2] = x; +} + +void +construct_lane_4 (long long **py, v2di **pz) +{ + long long *y = *py; + v2di *z = *pz; + long long y0 = y[0] + 1; + long long y1 = y[1] + 2; + v2di x = {y0, y1}; + z[2] = x; +} + /* We can use the load_pair_lanes pattern to vec_concat two DI/DF values from consecutive memory into a 2-element vector by using a Q-reg LDR. */ -/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 1 { xfail ilp32 } } } */ -/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 1 { xfail ilp32 } } } */ -/* { dg-final { scan-assembler-not "ins\t" { xfail ilp32 } } } */ +/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-not "ins\t" } } */