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[AArch64] PR target/71663 Improve Vector Initializtion

Message ID 58FF0803.5070007@foss.arm.com
State New
Headers show

Commit Message

Kyrill Tkachov April 25, 2017, 8:25 a.m. UTC 
Hi Naveen,

On 09/12/16 07:02, Hurugalawadi, Naveen wrote:
> Hi,
>
> Sorry. Missed out the testcase in patch submission.
> Added the missing testcase along with the ChangeLog.
> Please review the same and let us know if thats okay?

It would be useful if you expanded a bit on the approach used to
generate the improved codegen, or at least show for the testcase
what code was generated before this patch and what is generated
after this patch.

> 2016-12-09  Andrew PInski  <apinski@cavium.com>
>
> gcc
>          * config/aarch64/aarch64.c (aarch64_expand_vector_init):
>          Improve vector initialization code gen.
> gcc/testsuite
>          * gcc.target/aarch64/pr71663.c: New Testcase.

+  /* If there is only varables, try to optimize
+     the inseration using dup for the most common element
+     followed by insertations. */

Some typos: s/is only varables/are only variable elements/, s/inseration/insertion/,
s/insertations/insertions/.

  +  if (n_var == n_elts && n_elts <= 16)



Cheers,
Kyrill
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Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/pr71663.c b/gcc/testsuite/gcc.target/aarch64/pr71663.c
new file mode 100644
index 0000000..c8df847
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr71663.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+vector float combine (float a, float b, float c, float d)
+{
+  return (vector float) { a, b, c, d };
+}

A large part of the aarch64.c hunk of your patch deals with finding the most commonly-occuring
element in the vector of variables, yet in your testcase all variables appear exactly once.
Perhaps worth adding a testcase where one of the vector elements appears more than the others?
I'd guess the codegen then would be better with this patch?