From patchwork Mon Dec 5 11:27:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 702692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tXMts5gLtz9t1d for ; Mon, 5 Dec 2016 22:27:48 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="rtGBVu9z"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=buwGPaP27rB8zTHq9 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sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_50, KAM_LOTSOFHASH, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=chip, Secure, joined, Builtin X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Dec 2016 11:27:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 564711570; Mon, 5 Dec 2016 03:27:25 -0800 (PST) Received: from [10.2.206.251] (e107157-lin.cambridge.arm.com [10.2.206.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 073083F483 for ; Mon, 5 Dec 2016 03:27:24 -0800 (PST) Subject: [arm-embedded][committed][PATCH 1/7] Add support for ARMv8-M's Secure Extensions flag and intrinsics To: gcc-patches@gcc.gnu.org References: <5796116C.6010100@arm.com> <579611FF.4090807@arm.com> <57BD7E4C.5080809@arm.com> <580F87B2.7090407@arm.com> <58107391.7070007@foss.arm.com> <5810A8F0.40702@foss.arm.com> <5811CEB2.50809@arm.com> <5811D079.5010004@foss.arm.com> From: "Andre Vieira (lists)" Message-ID: <58454F1B.7010408@arm.com> Date: Mon, 5 Dec 2016 11:27:23 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <5811D079.5010004@foss.arm.com> X-IsSubscribed: yes On 27/10/16 11:01, Kyrill Tkachov wrote: > > On 27/10/16 10:53, Andre Vieira (lists) wrote: >> On 26/10/16 14:00, Kyrill Tkachov wrote: >>> On 26/10/16 10:12, Kyrill Tkachov wrote: >>>> Hi Andre, thanks for resending them. >>>> >>>> On 25/10/16 17:26, Andre Vieira (lists) wrote: >>>>> On 24/08/16 12:00, Andre Vieira (lists) wrote: >>>>>> On 25/07/16 14:19, Andre Vieira (lists) wrote: >>>>>>> This patch adds the support of the '-mcmse' option to enable >>>>>>> ARMv8-M's >>>>>>> Security Extensions and supports the following intrinsics: >>>>>>> cmse_TT >>>>>>> cmse_TT_fptr >>>>>>> cmse_TTT >>>>>>> cmse_TTT_fptr >>>>>>> cmse_TTA >>>>>>> cmse_TTA_fptr >>>>>>> cmse_TTAT >>>>>>> cmse_TTAT_fptr >>>>>>> cmse_check_address_range >>>>>>> cmse_check_pointed_object >>>>>>> cmse_is_nsfptr >>>>>>> cmse_nsfptr_create >>>>>>> >>>>>>> It also defines the mandatory cmse_address_info struct and the >>>>>>> __ARM_FEATURE_CMSE macro. >>>>>>> See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security >>>>>>> Extensions: Requirements on Development Tools >>>>>>> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html). >>>>>>> >>>>>>> >>>>>>> >>>>>>> *** gcc/ChangeLog *** >>>>>>> 2016-07-25 Andre Vieira >>>>>>> Thomas Preud'homme >>>>>>> >>>>>>> * config.gcc (extra_headers): Added arm_cmse.h. >>>>>>> * config/arm/arm-arches.def (ARM_ARCH): >>>>>>> (armv8-m): Add FL2_CMSE. >>>>>>> (armv8-m.main): Likewise. >>>>>>> (armv8-m.main+dsp): Likewise. >>>>>>> * config/arm/arm-c.c >>>>>>> (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. >>>>>>> * config/arm/arm-protos.h >>>>>>> (arm_is_constant_pool_ref): Define FL2_CMSE. >>>>>>> * config/arm.c (arm_arch_cmse): New. >>>>>>> (arm_option_override): New error for unsupported cmse >>>>>>> target. >>>>>>> * config/arm/arm.h (arm_arch_cmse): New. >>>>>>> * config/arm/arm.opt (mcmse): New. >>>>>>> * doc/invoke.texi (ARM Options): Add -mcmse. >>>>>>> * config/arm/arm_cmse.h: New file. >>>>>>> >>>>>>> *** libgcc/ChangeLog *** >>>>>>> 2016-07-25 Andre Vieira >>>>>>> Thomas Preud'homme >>>>>>> >>>>>>> * config/arm/cmse.c: Likewise. >>>>>>> * config/arm/t-arm (HAVE_CMSE): New. >>>>>>> >>>>>>> *** gcc/testsuite/ChangeLog *** >>>>>>> 2016-07-25 Andre Vieira >>>>>>> Thomas Preud'homme >>>>>>> >>>>>>> * gcc.target/arm/cmse/cmse.exp: New. >>>>>>> * gcc.target/arm/cmse/cmse-1.c: New. >>>>>>> * gcc.target/arm/cmse/cmse-12.c: New. >>>>>>> * lib/target-supports.exp >>>>>>> (check_effective_target_arm_cmse_ok): New. >>> >>> Just remembered, new effective target checks should be documented in >>> sourcebuild.texi >>> Kyrill >>> >>>>>> Added more documentation as requested. >>>>>> >>>>>> This patch adds the support of the '-mcmse' option to enable >>>>>> ARMv8-M's >>>>>> Security Extensions and supports the following intrinsics: >>>>>> cmse_TT >>>>>> cmse_TT_fptr >>>>>> cmse_TTT >>>>>> cmse_TTT_fptr >>>>>> cmse_TTA >>>>>> cmse_TTA_fptr >>>>>> cmse_TTAT >>>>>> cmse_TTAT_fptr >>>>>> cmse_check_address_range >>>>>> cmse_check_pointed_object >>>>>> cmse_is_nsfptr >>>>>> cmse_nsfptr_create >>>>>> >>>>>> It also defines the mandatory cmse_address_info struct and the >>>>>> __ARM_FEATURE_CMSE macro. >>>>>> See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security >>>>>> Extensions: Requirements on Development Tools >>>>>> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html). >>>>>> >>>>>> >>>>>> >>>>>> *** gcc/ChangeLog *** >>>>>> 2016-07-xx Andre Vieira >>>>>> Thomas Preud'homme >>>>>> >>>>>> * config.gcc (extra_headers): Added arm_cmse.h. >>>>>> * config/arm/arm-arches.def (ARM_ARCH): >>>>>> (armv8-m): Add FL2_CMSE. >>>>>> (armv8-m.main): Likewise. >>>>>> (armv8-m.main+dsp): Likewise. >>>>>> * config/arm/arm-c.c >>>>>> (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. >>>>>> * config/arm/arm-protos.h >>>>>> (arm_is_constant_pool_ref): Define FL2_CMSE. >>>>>> * config/arm.c (arm_arch_cmse): New. >>>>>> (arm_option_override): New error for unsupported cmse >>>>>> target. >>>>>> * config/arm/arm.h (arm_arch_cmse): New. >>>>>> * config/arm/arm.opt (mcmse): New. >>>>>> * doc/invoke.texi (ARM Options): Add -mcmse. >>>>>> * doc/extend.texi (ARM ARMv8-M Security Extensions): Add >>>>>> section. >>>>>> * config/arm/arm_cmse.h: New file. >>>>>> >>>>>> *** libgcc/ChangeLog *** >>>>>> 2016-07-xx Andre Vieira >>>>>> Thomas Preud'homme >>>>>> * config/arm/cmse.c: Likewise. >>>>>> * config/arm/t-arm (HAVE_CMSE): New. >>>>>> >>>>>> >>>>>> *** gcc/testsuite/ChangeLog *** >>>>>> 2016-07-xx Andre Vieira >>>>>> Thomas Preud'homme >>>>>> >>>>>> * gcc.target/arm/cmse/cmse.exp: New. >>>>>> * gcc.target/arm/cmse/cmse-1.c: New. >>>>>> * gcc.target/arm/cmse/cmse-12.c: New. >>>>>> * lib/target-supports.exp >>>>>> (check_effective_target_arm_cmse_ok): New. >>>>>> >>>>> Hi, >>>>> >>>>> Rebased previous patch on top of trunk as requested. No changes to >>>>> ChangeLog. >>>>> >>>>> Cheers, >>>>> Andre >>>> diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h >>>> new file mode 100644 >>>> index >>>> 0000000000000000000000000000000000000000..b4232937c6ae04754a6bbc513b143672a4be5530 >>>> >>>> >>>> --- /dev/null >>>> +++ b/gcc/config/arm/arm_cmse.h >>>> >>>> >>>> >>>> + >>>> +#if __ARM_FEATURE_CMSE & 2 >>>> + >>>> +#define cmse_TTA_fptr(p) (__cmse_TTA_fptr ((__cmse_fptr)(p))) >>>> + >>>> +__extension__ static __inline __attribute__ ((__always_inline__)) >>>> +cmse_address_info_t >>>> +__cmse_TTA_fptr (__cmse_fptr __p) >>>> +__CMSE_TT_ASM (a) >>>> + >>>> +__extension__ static __inline __attribute__ ((__always_inline__)) >>>> +cmse_address_info_t >>>> +cmse_TTA (void *__p) >>>> +__CMSE_TT_ASM (a) >>>> + >>>> +#define cmse_TTAT_fptr(p) (__cmse_TTAT_fptr ((__cmse_fptr)(p))) >>>> + >>>> +__extension__ static __inline cmse_address_info_t >>>> +__attribute__ ((__always_inline__)) >>>> +__cmse_TTAT_fptr (__cmse_fptr __p) >>>> +__CMSE_TT_ASM (at) >>>> + >>>> +__extension__ static __inline cmse_address_info_t >>>> +__attribute__ ((__always_inline__)) >>>> +cmse_TTAT (void *__p) >>>> +__CMSE_TT_ASM (at) >>>> + >>>> +#define CMSE_AU_NONSECURE 2 >>>> +#define CMSE_MPU_NONSECURE 16 >>>> +#define CMSE_NONSECURE 18 >>>> + >>>> +#endif /* __ARM_FEATURE_CMSE & 2 */ >>>> + >>>> +#define CMSE_MPU_UNPRIV 4 >>>> +#define CMSE_MPU_READWRITE 1 >>>> +#define CMSE_MPU_READ 8 >>>> + >>>> +__extension__ void * >>>> +cmse_check_address_range (void *, size_t, int); >>>> + >>>> +#define cmse_check_pointed_object(p, f) \ >>>> + ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f))) >>>> + >>>> +#define cmse_nsfptr_create(p) ((typeof ((p))) ((intptr_t) (p) & ~1)) >>>> + >>>> +#define cmse_is_nsfptr(p) (!((intptr_t) (p) & 1)) >>>> + >>>> +#endif /* __ARM_FEATURE_CMSE & 1 */ >>>> >>>> From my reading of the spec >>>> (http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf) >>>> >>>> >>>> cmse_nsfptr_create and cmse_is_nsfptr should be defined if bit 1 of >>>> __ARM_FEATURE_CMSE is set. >>>> But in your patch they fall under the "#if __ARM_FEATURE_CMSE & 1" >>>> check which checks bit 0. >>>> They should be in the "__ARM_FEATURE_CMSE & 2" block. Please double >>>> check the other defines against the SPEC to make sure they >>>> match the feature bit in __ARM_FEATURE_CMSE. >>>> >>>> The patch is ok with that resolved if bootstrap and test on a normal >>>> arm-none-linux-gnueabihf configuration >>>> shows no problems. >>>> Thanks, >>>> Kyrill >>>> >> Hi, >> >> Reworked comments. >> >> Is this OK? > > Yes, thanks. > Please hold off committing until the whole series is approved. > Kyrill > >> Cheers, >> Andre >> >> *** gcc/ChangeLog *** >> 2016-10-27 Andre Vieira >> Thomas Preud'homme >> >> * config.gcc (extra_headers): Added arm_cmse.h. >> * config/arm/arm-arches.def (ARM_ARCH): >> (armv8-m): Add FL2_CMSE. >> (armv8-m.main): Likewise. >> (armv8-m.main+dsp): Likewise. >> * config/arm/arm-c.c >> (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. >> * config/arm/arm-protos.h >> (arm_is_constant_pool_ref): Define FL2_CMSE. >> * config/arm.c (arm_arch_cmse): New. >> (arm_option_override): New error for unsupported cmse target. >> * config/arm/arm.h (arm_arch_cmse): New. >> * config/arm/arm.opt (mcmse): New. >> * doc/invoke.texi (ARM Options): Add -mcmse. >> * config/arm/arm_cmse.h: New file. >> * doc/sourcebuild.texi (arm_cmse_ok): Add new effective target. >> >> *** libgcc/ChangeLog *** >> 2016-10-27 Andre Vieira >> Thomas Preud'homme >> >> * config/arm/cmse.c: Likewise. >> * config/arm/t-arm (HAVE_CMSE): New. >> >> *** gcc/testsuite/ChangeLog *** >> 2016-10-27 Andre Vieira >> Thomas Preud'homme >> >> * gcc.target/arm/cmse/cmse.exp: New. >> * gcc.target/arm/cmse/cmse-1.c: New. >> * gcc.target/arm/cmse/cmse-12.c: New. >> * lib/target-supports.exp >> (check_effective_target_arm_cmse_ok): New. >> > Hi, Backported this to the embedded-6-branch in revision r243246. Cheers, Andre gcc/ChangeLog.arm: 2016-12-05 Andre Vieira Backport from mainline 2016-12-02 Andre Vieira Thomas Preud'homme * config.gcc (extra_headers): Added arm_cmse.h. * config/arm/arm-arches.def (ARM_ARCH): (armv8-m): Add FL2_CMSE. (armv8-m.main): Likewise. (armv8-m.main+dsp): Likewise. * config/arm/arm-c.c (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. * config/arm/arm-flags.h: Define FL2_CMSE. * config/arm.c (arm_arch_cmse): New. (arm_option_override): New error for unsupported cmse target. * config/arm/arm.h (arm_arch_cmse): New. * config/arm/arm.opt (mcmse): New. * config/arm/arm_cmse.h: New file. * doc/invoke.texi (ARM Options): Add -mcmse. * doc/sourcebuild.texi (arm_cmse_ok): Add new effective target. * doc/extend.texi: Add ARMv8-M Security Extensions entry. gcc/testsuite/ChangeLog.arm: 2016-12-05 Andre Vieira Backport from mainline 2016-12-02 Andre Vieira Thomas Preud'homme * gcc.target/arm/cmse/cmse.exp: New. * gcc.target/arm/cmse/cmse-1.c: New. * gcc.target/arm/cmse/cmse-12.c: New. * lib/target-supports.exp (check_effective_target_arm_cmse_ok): New. libgcc/ChangeLog.arm: 2016-12-05 Andre Vieira Backport from mainline 2016-12-02 Andre Vieira Thomas Preud'homme * config/arm/t-arm (HAVE_CMSE): New. * config/arm/cmse.c: New. diff --git a/gcc/ChangeLog.arm b/gcc/ChangeLog.arm index d30cbcd8b5b6b6019b5f23d6e8d8b903ef7026c8..98704eb438dadd73cf793da5a7b8266b5e9ef267 100644 --- a/gcc/ChangeLog.arm +++ b/gcc/ChangeLog.arm @@ -1,3 +1,26 @@ +2016-12-05 Andre Vieira + + Backport from mainline + 2016-12-02 Andre Vieira + Thomas Preud'homme + + * config.gcc (extra_headers): Added arm_cmse.h. + * config/arm/arm-arches.def (ARM_ARCH): + (armv8-m): Add FL2_CMSE. + (armv8-m.main): Likewise. + (armv8-m.main+dsp): Likewise. + * config/arm/arm-c.c + (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro. + * config/arm/arm-flags.h: Define FL2_CMSE. + * config/arm.c (arm_arch_cmse): New. + (arm_option_override): New error for unsupported cmse target. + * config/arm/arm.h (arm_arch_cmse): New. + * config/arm/arm.opt (mcmse): New. + * config/arm/arm_cmse.h: New file. + * doc/invoke.texi (ARM Options): Add -mcmse. + * doc/sourcebuild.texi (arm_cmse_ok): Add new effective target. + * doc/extend.texi: Add ARMv8-M Security Extensions entry. + 2016-11-22 Thomas Preud'homme Backport from mainline diff --git a/gcc/config.gcc b/gcc/config.gcc index 9c29e50cb1d2e6c02a02c8554b5e880ef9e6ccc0..607b526dac650c6ab917b5b07e2de3e0c2ecc9a7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -327,7 +327,7 @@ arc*-*-*) arm*-*-*) cpu_type=arm extra_objs="arm-builtins.o aarch-common.o" - extra_headers="mmintrin.h arm_neon.h arm_acle.h" + extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_cmse.h" target_type_format_char='%' c_target_objs="arm-c.o" cxx_target_objs="arm-c.o" diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index 59dac9a2304a92e9cac7c5ccdf1f0b655606fe15..1d2442970540948056c33f67288e1b4a281d7657 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -63,11 +63,11 @@ ARM_ARCH("armv8.1-a+crc",cortexa53, 8A, ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A)) ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE, - ARM_FSET_MAKE_CPU1 ( FL_FOR_ARCH8M_BASE)) + ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE)) ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN, - ARM_FSET_MAKE_CPU1(FL_CO_PROC | FL_FOR_ARCH8M_MAIN)) + ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE)) ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN, - ARM_FSET_MAKE_CPU1(FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN)) + ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE)) ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)) ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)) diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 4fbdfc50d03507380e4fb59883923a81d9367489..c8ab1cb2377ebe7e8e96802f05142b33bb8008cb 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -76,6 +76,14 @@ arm_cpu_builtins (struct cpp_reader* pfile) def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); + if (arm_arch8 && !arm_arch_notm) + { + if (arm_arch_cmse && use_cmse) + builtin_define_with_int_value ("__ARM_FEATURE_CMSE", 3); + else + builtin_define ("__ARM_FEATURE_CMSE"); + } + if (TARGET_ARM_FEATURE_LDREX) builtin_define_with_int_value ("__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h index 3feef51896a6de8c45f7e82aa252147f56b32b7a..d6709af5daab4d959990b2c6611bc3c1bc33a7f9 100644 --- a/gcc/config/arm/arm-flags.h +++ b/gcc/config/arm/arm-flags.h @@ -67,6 +67,7 @@ #define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */ #define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */ +#define FL2_CMSE (1U << 3) /* ARMv8-M Security Extensions. */ /* Flags that only effect tuning, not available instructions. */ #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 291d82d48c28d19c72aec569a05f2765c0809cdb..de9ad3e6a2df5103519ec16fcecdac8861a1cdfc 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -519,6 +519,9 @@ extern bool arm_disable_literal_pool; /* Nonzero if chip supports the ARMv8 CRC instructions. */ extern int arm_arch_crc; +/* Nonzero if chip supports the ARMv8-M Security Extensions. */ +extern int arm_arch_cmse; + #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APCS_FRAME) #endif diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index cc0bc7a669467ac7d0c1f9edcf70c4b0b8431690..7050f4897ddd9886d6c5377ca9c3e2764e2dff25 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -906,6 +906,9 @@ int arm_condexec_masklen = 0; /* Nonzero if chip supports the ARMv8 CRC instructions. */ int arm_arch_crc = 0; +/* Nonzero if chip supports the ARMv8-M security extensions. */ +int arm_arch_cmse = 0; + /* Nonzero if the core has a very small, high-latency, multiply unit. */ int arm_m_profile_small_mul = 0; @@ -3209,6 +3212,7 @@ arm_option_override (void) arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE); arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32); + arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE); arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL); /* V5 code we generate is completely interworking capable, so we turn off @@ -3462,6 +3466,9 @@ arm_option_override (void) if (target_slow_flash_data || target_pure_code) arm_disable_literal_pool = true; + if (use_cmse && !arm_arch_cmse) + error ("target CPU does not support ARMv8-M Security Extensions"); + /* Disable scheduling fusion by default if it's not armv7 processor or doesn't prefer ldrd/strd. */ if (flag_schedule_fusion == 2 diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 35f047e2de1659c2b426cf42dbbdae5be62cbfef..5fb645df71b93960e8cda38c4b5b1d9d37df125c 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -109,6 +109,10 @@ mfloat-abi= Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI) Specify if floating point hardware should be used. +mcmse +Target RejectNegative Var(use_cmse) +Specify that the compiler should target secure code as per ARMv8-M Security Extensions. + Enum Name(float_abi_type) Type(enum float_abi_type) Known floating-point ABIs (for use with the -mfloat-abi= option): diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h new file mode 100644 index 0000000000000000000000000000000000000000..894343bb835b61e09c14668d45aa43a8693fd011 --- /dev/null +++ b/gcc/config/arm/arm_cmse.h @@ -0,0 +1,192 @@ +/* ARMv8-M Secure Extensions intrinsics include file. + + Copyright (C) 2015-2016 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + + +#ifndef _GCC_ARM_CMSE_H +#define _GCC_ARM_CMSE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if __ARM_FEATURE_CMSE & 1 + +#include +#include + +#ifdef __ARM_BIG_ENDIAN + +typedef union { + struct cmse_address_info { +#if __ARM_FEATURE_CMSE & 2 + unsigned idau_region:8; + unsigned idau_region_valid:1; + unsigned secure:1; + unsigned nonsecure_readwrite_ok:1; + unsigned nonsecure_read_ok:1; +#else + unsigned :12; +#endif + unsigned readwrite_ok:1; + unsigned read_ok:1; +#if __ARM_FEATURE_CMSE & 2 + unsigned sau_region_valid:1; +#else + unsigned :1; +#endif + unsigned mpu_region_valid:1; +#if __ARM_FEATURE_CMSE & 2 + unsigned sau_region:8; +#else + unsigned :8; +#endif + unsigned mpu_region:8; + } flags; + unsigned value; +} cmse_address_info_t; + +#else + +typedef union { + struct cmse_address_info { + unsigned mpu_region:8; +#if __ARM_FEATURE_CMSE & 2 + unsigned sau_region:8; +#else + unsigned :8; +#endif + unsigned mpu_region_valid:1; +#if __ARM_FEATURE_CMSE & 2 + unsigned sau_region_valid:1; +#else + unsigned :1; +#endif + unsigned read_ok:1; + unsigned readwrite_ok:1; +#if __ARM_FEATURE_CMSE & 2 + unsigned nonsecure_read_ok:1; + unsigned nonsecure_readwrite_ok:1; + unsigned secure:1; + unsigned idau_region_valid:1; + unsigned idau_region:8; +#else + unsigned :12; +#endif + } flags; + unsigned value; +} cmse_address_info_t; + +#endif /* __ARM_BIG_ENDIAN */ + +#define cmse_TT_fptr(p) (__cmse_TT_fptr ((__cmse_fptr)(p))) + +typedef void (*__cmse_fptr)(void); + +#define __CMSE_TT_ASM(flags) \ +{ \ + cmse_address_info_t __result; \ + __asm__ ("tt" # flags " %0,%1" \ + : "=r"(__result) \ + : "r"(__p) \ + : "memory"); \ + return __result; \ +} + +__extension__ static __inline __attribute__ ((__always_inline__)) +cmse_address_info_t +__cmse_TT_fptr (__cmse_fptr __p) +__CMSE_TT_ASM () + +__extension__ static __inline __attribute__ ((__always_inline__)) +cmse_address_info_t +cmse_TT (void *__p) +__CMSE_TT_ASM () + +#define cmse_TTT_fptr(p) (__cmse_TTT_fptr ((__cmse_fptr)(p))) + +__extension__ static __inline __attribute__ ((__always_inline__)) +cmse_address_info_t +__cmse_TTT_fptr (__cmse_fptr __p) +__CMSE_TT_ASM (t) + +__extension__ static __inline __attribute__ ((__always_inline__)) +cmse_address_info_t +cmse_TTT (void *__p) +__CMSE_TT_ASM (t) + +#if __ARM_FEATURE_CMSE & 2 + +#define cmse_TTA_fptr(p) (__cmse_TTA_fptr ((__cmse_fptr)(p))) + +__extension__ static __inline __attribute__ ((__always_inline__)) +cmse_address_info_t +__cmse_TTA_fptr (__cmse_fptr __p) +__CMSE_TT_ASM (a) + +__extension__ static __inline __attribute__ ((__always_inline__)) +cmse_address_info_t +cmse_TTA (void *__p) +__CMSE_TT_ASM (a) + +#define cmse_TTAT_fptr(p) (__cmse_TTAT_fptr ((__cmse_fptr)(p))) + +__extension__ static __inline cmse_address_info_t +__attribute__ ((__always_inline__)) +__cmse_TTAT_fptr (__cmse_fptr __p) +__CMSE_TT_ASM (at) + +__extension__ static __inline cmse_address_info_t +__attribute__ ((__always_inline__)) +cmse_TTAT (void *__p) +__CMSE_TT_ASM (at) + +#define CMSE_AU_NONSECURE 2 +#define CMSE_MPU_NONSECURE 16 +#define CMSE_NONSECURE 18 + +#define cmse_nsfptr_create(p) ((typeof ((p))) ((intptr_t) (p) & ~1)) + +#define cmse_is_nsfptr(p) (!((intptr_t) (p) & 1)) + +#endif /* __ARM_FEATURE_CMSE & 2 */ + +#define CMSE_MPU_UNPRIV 4 +#define CMSE_MPU_READWRITE 1 +#define CMSE_MPU_READ 8 + +__extension__ void * +cmse_check_address_range (void *, size_t, int); + +#define cmse_check_pointed_object(p, f) \ + ((typeof ((p))) cmse_check_address_range ((p), sizeof (*(p)), (f))) + +#endif /* __ARM_FEATURE_CMSE & 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GCC_ARM_CMSE_H */ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ee2715d7ea62238f43eca099f04dbcb26a3af459..b582d5300d464ac3783c1fe60a73aca2527a9575 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -11416,6 +11416,7 @@ instructions, but allow the compiler to schedule those calls. * ARM iWMMXt Built-in Functions:: * ARM C Language Extensions (ACLE):: * ARM Floating Point Status and Control Intrinsics:: +* ARM ARMv8-M Security Extensions:: * AVR Built-in Functions:: * Blackfin Built-in Functions:: * FR-V Built-in Functions:: @@ -12260,6 +12261,31 @@ unsigned int __builtin_arm_get_fpscr () void __builtin_arm_set_fpscr (unsigned int) @end smallexample +@node ARM ARMv8-M Security Extensions +@subsection ARM ARMv8-M Security Extensions + +GCC implements the ARMv8-M Security Extensions as described in the ARMv8-M +Security Extensions: Requiremenets on Development Tools Engineering +Specification, which can be found at +@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}. + +As part of the Security Extensions GCC implements the intrinsics below. FPTR +is used here to mean any function pointer type. + +@smallexample +cmse_address_info_t cmse_TT (void *) +cmse_address_info_t cmse_TT_fptr (FPTR) +cmse_address_info_t cmse_TTT (void *) +cmse_address_info_t cmse_TTT_fptr (FPTR) +cmse_address_info_t cmse_TTA (void *) +cmse_address_info_t cmse_TTA_fptr (FPTR) +cmse_address_info_t cmse_TTAT (void *) +cmse_address_info_t cmse_TTAT_fptr (FPTR) +void * cmse_check_address_range (void *, size_t, int) +typeof(p) cmse_nsfptr_create (FPTR p) +intptr_t cmse_is_nsfptr (FPTR) +@end smallexample + @node AVR Built-in Functions @subsection AVR Built-in Functions diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3112651f82790a2236042ed9a6791c78cf311d21..2f0ec8a6ced999fad5585bccf48f7534daa09189 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -633,7 +633,8 @@ Objective-C and Objective-C++ Dialects}. -mslow-flash-data @gol -masm-syntax-unified @gol -mrestrict-it @gol --mpure-code} +-mpure-code @gol +-mcmse} @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol @@ -14332,6 +14333,11 @@ Additionally, when compiling for ELF object format give all text sections the ELF processor-specific section attribute @code{SHF_ARM_PURECODE}. This option is only available when generating non-pic code for ARMv7-M targets. +@item -mcmse +@opindex mcmse +Generate secure code as per the "ARMv8-M Security Extensions: Requirements on +Development Tools Engineering Specification", which can be found on +@url{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}. @end table @node AVR Options diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 74a679c64f4e575aecaa7dda93a19635a3595f6a..7f74d87b144be530a1f012819aed63519d7e2cbf 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1609,6 +1609,10 @@ and @code{MOVT} instructions available. ARM target generates Thumb-1 code for @code{-mthumb} with @code{CBZ} and @code{CBNZ} instructions available. +@item arm_cmse_ok +ARM target supports ARMv8-M Security Extensions, enabled by the @code{-mcmse} +option. + @end table @subsubsection AArch64-specific attributes diff --git a/gcc/testsuite/ChangeLog.arm b/gcc/testsuite/ChangeLog.arm index 637ad1364c0cf2f4544f13c1b20521be804cc753..767b44aec61c90663ed7540e34c0e24da8c4835c 100644 --- a/gcc/testsuite/ChangeLog.arm +++ b/gcc/testsuite/ChangeLog.arm @@ -1,3 +1,15 @@ +2016-12-05 Andre Vieira + + Backport from mainline + 2016-12-02 Andre Vieira + Thomas Preud'homme + + * gcc.target/arm/cmse/cmse.exp: New. + * gcc.target/arm/cmse/cmse-1.c: New. + * gcc.target/arm/cmse/cmse-12.c: New. + * lib/target-supports.exp + (check_effective_target_arm_cmse_ok): New. + 2016-11-22 Thomas Preud'homme Backport from mainline diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c new file mode 100644 index 0000000000000000000000000000000000000000..d5b9a2d9d59569de170da814ae660e9fb2b943e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-Os -mcmse -fdump-rtl-expand" } */ + +#include + +extern int a; +extern int bar (void); + +int foo (char * p) +{ + cmse_address_info_t cait; + + cait = cmse_TT (&a); + if (cait.flags.mpu_region) + a++; + + cait = cmse_TT_fptr (&bar); + if (cait.flags.mpu_region) + a+= bar (); + + cait = cmse_TTA (&a); + if (cait.flags.mpu_region) + a++; + + cait = cmse_TTA_fptr (&bar); + if (cait.flags.mpu_region) + a+= bar (); + + cait = cmse_TTT (&a); + if (cait.flags.mpu_region) + a++; + + cait = cmse_TTT_fptr (&bar); + if (cait.flags.mpu_region) + a+= bar (); + + cait = cmse_TTAT (&a); + if (cait.flags.mpu_region) + a++; + + cait = cmse_TTAT_fptr (&bar); + if (cait.flags.mpu_region) + a+= bar (); + + p = (char *) cmse_check_address_range ((void *) p, sizeof (char), 0); + p = (char *) cmse_check_address_range ((void *) p, sizeof (char), + CMSE_MPU_UNPRIV); + p = (char *) cmse_check_address_range ((void *) p, sizeof (char), + CMSE_MPU_READWRITE); + p = (char *) cmse_check_address_range ((void *) p, sizeof (char), + CMSE_MPU_UNPRIV | CMSE_MPU_READ); + p = (char *) cmse_check_address_range ((void *) p, sizeof (char), + CMSE_AU_NONSECURE + | CMSE_MPU_NONSECURE); + p = (char *) cmse_check_address_range ((void *) p, sizeof (char), + CMSE_NONSECURE | CMSE_MPU_UNPRIV); + + p = (char *) cmse_check_pointed_object (p, CMSE_NONSECURE | CMSE_MPU_UNPRIV); + + return a; +} +/* { dg-final { scan-assembler-times "\ttt " 2 } } */ +/* { dg-final { scan-assembler-times "ttt " 2 } } */ +/* { dg-final { scan-assembler-times "tta " 2 } } */ +/* { dg-final { scan-assembler-times "ttat " 2 } } */ +/* { dg-final { scan-assembler-times "bl.cmse_check_address_range" 7 } } */ +/* { dg-final { scan-assembler-not "cmse_check_pointed_object" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse-12.c b/gcc/testsuite/gcc.target/arm/cmse/cmse-12.c new file mode 100644 index 0000000000000000000000000000000000000000..87a2f1363a4e4bd817503e79e504980210e722c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse-12.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mcmse" } */ +#include + +char * +foo (char * p) +{ + if (!cmse_is_nsfptr (p)) + return cmse_nsfptr_create (p); +} + +/* Checks for saving and clearing prior to function call. */ +/* { dg-final { scan-assembler-not "cmse_is_nsfptr" } } */ +/* { dg-final { scan-assembler-not "cmse_nsfptr_create" } } */ diff --git a/gcc/testsuite/gcc.target/arm/cmse/cmse.exp b/gcc/testsuite/gcc.target/arm/cmse/cmse.exp new file mode 100644 index 0000000000000000000000000000000000000000..f797dba1901720e04249d61078c1cbf2a3e436a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cmse/cmse.exp @@ -0,0 +1,50 @@ +# Copyright (C) 1997-2016 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite for ARMv8-M Security Extensions using the `dg.exp' driver. + +# Load support procs. +load_lib gcc-dg.exp + +# Exit immediately if the target does not support -mcmse. +if ![check_effective_target_arm_cmse_ok] then { + return +} + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +set saved-dg-do-what-default ${dg-do-what-default} +set dg-do-what-default "assemble" + +set saved-lto_torture_options ${LTO_TORTURE_OPTIONS} +set LTO_TORTURE_OPTIONS "" + +# These are for both baseline and mainline. +gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] \ + "" $DEFAULT_CFLAGS + +set LTO_TORTURE_OPTIONS ${saved-lto_torture_options} +set dg-do-what-default ${saved-dg-do-what-default} + +# All done. +dg-finish diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 5fd027ccccc18fc4b0e0f50bca8380dafde3a271..a1d786b04466574b4f7ee19d4d6fa13464917d91 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3397,6 +3397,19 @@ proc check_effective_target_arm_thumb1_cbz_ok {} { } } +# Return 1 if this is an ARM target where ARMv8-M Security Extensions is +# available. + +proc check_effective_target_arm_cmse_ok {} { + return [check_no_compiler_messages arm_cmse object { + int + foo (void) + { + asm ("bxns r0"); + } + } "-mcmse"]; +} + # Return 1 if this compilation turns on string_ops_prefer_neon on. proc check_effective_target_arm_tune_string_ops_prefer_neon { } { diff --git a/libgcc/ChangeLog.arm b/libgcc/ChangeLog.arm index 0b6e290bdc8fdc3a7d995e0da18a38785afcc666..50b4ce5f0e8a32c51c7831291852caccad14e9c9 100644 --- a/libgcc/ChangeLog.arm +++ b/libgcc/ChangeLog.arm @@ -1,3 +1,12 @@ +2016-12-05 Andre Vieira + + Backport from mainline + 2016-12-02 Andre Vieira + Thomas Preud'homme + + * config/arm/t-arm (HAVE_CMSE): New. + * config/arm/cmse.c: New. + 2016-07-12 Andre Vieira Backport from mainline diff --git a/libgcc/config/arm/cmse.c b/libgcc/config/arm/cmse.c new file mode 100644 index 0000000000000000000000000000000000000000..fe3a22967c8536f2a8c05b58627f964d3fb1d345 --- /dev/null +++ b/libgcc/config/arm/cmse.c @@ -0,0 +1,108 @@ +/* ARMv8-M Security Extensions routines. + Copyright (C) 2015-2016 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 3, or (at your option) any + later version. + + This file is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + + +#if __ARM_FEATURE_CMSE & 1 + +#include + +/* ARM intrinsic function to perform a permission check on a given + address range. See ACLE changes for ARMv8-M. */ + +void * +cmse_check_address_range (void *p, size_t size, int flags) +{ + cmse_address_info_t permb, perme; + char *pb = (char *) p, *pe; + + /* Check if the range wraps around. */ + if (UINTPTR_MAX - (uintptr_t) p < size) + return NULL; + + /* Check if an unknown flag is present. */ + int known = CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE | CMSE_MPU_READ; + int known_secure_level = CMSE_MPU_UNPRIV; +#if __ARM_FEATURE_CMSE & 2 + known |= CMSE_AU_NONSECURE | CMSE_MPU_NONSECURE; + known_secure_level |= CMSE_MPU_NONSECURE; +#endif + if (flags & (~known)) + return NULL; + + /* Execute the right variant of the TT instructions. */ + pe = pb + size - 1; + const int singleCheck = (((uintptr_t) pb ^ (uintptr_t) pe) < 32); + switch (flags & known_secure_level) + { + case 0: + permb = cmse_TT (pb); + perme = singleCheck ? permb : cmse_TT (pe); + break; + case CMSE_MPU_UNPRIV: + permb = cmse_TTT (pb); + perme = singleCheck ? permb : cmse_TTT (pe); + break; +#if __ARM_FEATURE_CMSE & 2 + case CMSE_MPU_NONSECURE: + permb = cmse_TTA (pb); + perme = singleCheck ? permb : cmse_TTA (pe); + break; + case CMSE_MPU_UNPRIV | CMSE_MPU_NONSECURE: + permb = cmse_TTAT (pb); + perme = singleCheck ? permb : cmse_TTAT (pe); + break; +#endif + default: + /* Invalid flag, eg. CMSE_MPU_NONSECURE specified but + __ARM_FEATURE_CMSE & 2 == 0. */ + return NULL; + } + + /* Check that the range does not cross MPU, SAU, or IDAU boundaries. */ + if (permb.value != perme.value) + return NULL; + + /* Check the permissions on the range. */ + switch (flags & (~known_secure_level)) + { +#if __ARM_FEATURE_CMSE & 2 + case CMSE_MPU_READ | CMSE_MPU_READWRITE | CMSE_AU_NONSECURE: + case CMSE_MPU_READWRITE | CMSE_AU_NONSECURE: + return permb.flags.nonsecure_readwrite_ok ? p : NULL; + case CMSE_MPU_READ | CMSE_AU_NONSECURE: + return permb.flags.nonsecure_read_ok ? p : NULL; + case CMSE_AU_NONSECURE: + return permb.flags.secure ? NULL : p; +#endif + case CMSE_MPU_READ | CMSE_MPU_READWRITE: + case CMSE_MPU_READWRITE: + return permb.flags.readwrite_ok ? p : NULL; + case CMSE_MPU_READ: + return permb.flags.read_ok ? p : NULL; + default: + return NULL; + } +} + + +#endif /* __ARM_FEATURE_CMSE & 1. */ diff --git a/libgcc/config/arm/t-arm b/libgcc/config/arm/t-arm index 4e17e99b4a53bbafc0f1f8dddd02000f0e8f4f48..5618143bfd0f02b170db3f9e4c0a15cecb403cec 100644 --- a/libgcc/config/arm/t-arm +++ b/libgcc/config/arm/t-arm @@ -1,3 +1,15 @@ LIB1ASMSRC = arm/lib1funcs.S LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \ _thumb1_case_uhi _thumb1_case_si + +HAVE_CMSE:=$(findstring __ARM_FEATURE_CMSE,$(shell $(gcc_compile_bare) -dM -E - /dev/null),) +CMSE_OPTS:=-mcmse +endif + +ifdef HAVE_CMSE +libgcc-objects += cmse.o cmse_nonsecure_call.o + +cmse.o: $(srcdir)/config/arm/cmse.c + $(gcc_compile) -c $(CMSE_OPTS) $< +endif