From patchwork Wed Nov 16 16:57:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 695702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tJr6V1XGkz9s2Q for ; Thu, 17 Nov 2016 03:57:52 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ngIo2FoW"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=KQrjYISnEpd+rvvBBrIhJGZe0rGSRZg8mwZW09VCgOa YTorbp6oQMklL8eezNAaiQKRuQtuIAakgyyNX9dQ4CJi2wGINoRLFZyAwYTfLNwa afS8DA+RAecE3vSTpowirtLIDrTxeKDlDQW4xOPr6N3431UNkfKX5B1HJn5qN4xk = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=0S2Qud1V0gDM1Ry7T9oiNCvujj0=; b=ngIo2FoWWSVzFw6q1 bdfvmedsnKqJ5VTHmvMUA2Nr06kr+pilMozbjJfe5p1UbSoCRvItVgL3KtWaGHxL Za12THxWCSh0qc3vF62om1MbVyNph5UoYLUsgVxHlFJL+s4p1u3I1Sfh/RdTn1U6 pgKWg4W4B49OyTwTk7AtY+5qCg= Received: (qmail 73877 invoked by alias); 16 Nov 2016 16:57:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73855 invoked by uid 89); 16 Nov 2016 16:57:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Hx-languages-length:2738 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 16 Nov 2016 16:57:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E50516; Wed, 16 Nov 2016 08:57:31 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8FBCB3F218; Wed, 16 Nov 2016 08:57:30 -0800 (PST) Message-ID: <582C8FF9.9070603@foss.arm.com> Date: Wed, 16 Nov 2016 16:57:29 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] PR target/78362: Make sure to only take REGNO of a register Hi all, As the PR says we have an RTL checking failure that occurs when building libgcc for aarch64. The expander code for addsi3 takes the REGNO of a SUBREG in operands[1]. The three operands in the failing case are: {(reg:SI 78), (subreg:SI (reg:DI 77) 0), (subreg:SI (reg:DI 73 [ ivtmp.9 ]) 0)} According to the documentation of register_operand (which is the predicate for operands[1]), operands[1] can be a REG or a SUBREG. If it's a subreg it may also contain a MEM before reload (because it is guaranteed to be reloaded into a register later). Anyway, the bottom line is that we have to be careful when taking REGNO of expressions during expand-time. This patch extracts the inner rtx in case we have a SUBREG and checks that it's a REG before checking its REGNO. Bootstrapped and tested on aarch64-none-linux-gnu. Tested aarch64-none-elf with RTL checking enabled (without this patch that doesn't build). Ok for trunk? Thanks, Kyrill 2016-11-16 Kyrylo Tkachov PR target/78362 * config/aarch64/aarch64.md (add3): Extract inner expression from a subreg in operands[1] and don't call REGNO on a non-reg expression when deciding to force operands[2] into a reg. 2016-11-16 Kyrylo Tkachov PR target/78362 * gcc.c-torture/compile/pr78362.c: New test. commit 068224c568d6f06f68512f12ecebea8bfc873fe9 Author: Kyrylo Tkachov Date: Tue Nov 15 14:52:33 2016 +0000 [AArch64] PR target/78362: Make sure to only take REGNO of a register diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9e5eee9..1dcb6b2 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1611,11 +1611,15 @@ (define_expand "add3" (match_operand:GPI 2 "aarch64_pluslong_operand" "")))] "" { + /* If operands[1] is a subreg extract the inner RTX. */ + rtx op1 = REG_P (operands[1]) ? operands[1] : SUBREG_REG (operands[1]); + /* If the constant is too large for a single instruction and isn't frame based, split off the immediate so it is available for CSE. */ if (!aarch64_plus_immediate (operands[2], mode) && can_create_pseudo_p () - && !REGNO_PTR_FRAME_P (REGNO (operands[1]))) + && (!REG_P (op1) + || !REGNO_PTR_FRAME_P (REGNO (op1)))) operands[2] = force_reg (mode, operands[2]); }) diff --git a/gcc/testsuite/gcc.c-torture/compile/pr78362.c b/gcc/testsuite/gcc.c-torture/compile/pr78362.c new file mode 100644 index 0000000..66eea7d --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr78362.c @@ -0,0 +1,11 @@ +/* PR target/78362. */ + +long a; + +void +foo (void) +{ + for (;; a--) + if ((int) a) + break; +}