From patchwork Mon Apr 25 19:19:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evandro Menezes X-Patchwork-Id: 614598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qtwzV5Wtzz9t47 for ; Tue, 26 Apr 2016 05:20:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=TPTAUOQY; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=sIIvhVj1q9plYPtE2 6yIDFqOp8fdC8PFz69Gy/Hx7+E0TJ6Px56AXXUI6XcsiAJ1fu5J2D9jGQhaLLkUi USBNUyM0CDHYnKg9i5C/2CuM2+tvpkpmTgoSH49r+3C3YRiBHTjS6PvzlV/L/ocy ljafpwjgRU7KD3wgE7L5iUL8qw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=RgQ1CLonutAeNTDI8dAODvq EtLU=; b=TPTAUOQYjU9O0xwh4P1pJcyY+WwCbdPCwIiv3cKFpzGP9dmm10H/tjY SAjKJk3hhNTyPdbpywmqmeN0LMjz8qyr2LAaxDT0+q3nqySOEr4OZYX5PkOqvf0a bFv9RZgjxiXvBcJEZ8rVCS/cf1ttWz1YUUeXnrJpnUleSKZag86Q= Received: (qmail 23125 invoked by alias); 25 Apr 2016 19:20:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22574 invoked by uid 89); 25 Apr 2016 19:20:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=0h, sfmode, general_operand, sk:nonimme X-HELO: usmailout4.samsung.com Received: from mailout4.w2.samsung.com (HELO usmailout4.samsung.com) (211.189.100.14) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 25 Apr 2016 19:19:58 +0000 Received: from uscpsbgm1.samsung.com (u114.gpu85.samsung.co.kr [203.254.195.114]) by usmailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O670031AF18B260@usmailout4.samsung.com> for gcc-patches@gcc.gnu.org; Mon, 25 Apr 2016 15:19:56 -0400 (EDT) Received: from ussync3.samsung.com ( [203.254.195.83]) by uscpsbgm1.samsung.com (USCPMTA) with SMTP id 10.56.04845.CDD6E175; Mon, 25 Apr 2016 15:19:56 -0400 (EDT) Received: from [172.31.207.194] ([105.140.31.10]) by ussync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O670067HF164I90@ussync3.samsung.com>; Mon, 25 Apr 2016 15:19:56 -0400 (EDT) Subject: Re: [PATCH][AArch64] Replace insn to zero up SIMD registers To: James Greenhalgh References: <56D0D50E.8030802@samsung.com> <56D4D02C.6030309@samsung.com> <56D5E8B6.1090900@samsung.com> <56E0972F.3060207@samsung.com> <20160310132327.GA38844@arm.com> <56E1A061.5080901@samsung.com> <56E1A18F.5000006@samsung.com> <20160310163736.GA8272@arm.com> Cc: Wilco Dijkstra , "gcc-patches@gcc.gnu.org" , nd , Marcus Shawcroft , Kyrylo Tkachov , richard.earnshaw@arm.com From: Evandro Menezes Message-id: <571E6DD9.9010401@samsung.com> Date: Mon, 25 Apr 2016 14:19:53 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-version: 1.0 In-reply-to: <20160310163736.GA8272@arm.com> Content-type: multipart/mixed; boundary=------------000709020202000105040406 X-IsSubscribed: yes On 03/10/16 10:37, James Greenhalgh wrote: > On Thu, Mar 10, 2016 at 10:32:15AM -0600, Evandro Menezes wrote: >>> I agree to postpone until GCC 7. >>> >>> [AArch64] Replace insn to zero up SIMD registers >>> >>> gcc/ >>> * config/aarch64/aarch64.md >>> (*movhf_aarch64): Add "movi %0, #0" to zero up register. >>> (*movsf_aarch64): Likewise and add "simd" attributes. >>> (*movdf_aarch64): Likewise. >>> >>> This patch removes the FP attributes from the HF, SF, DF, TF moves. > Thanks for sticking with it. This is OK for GCC 7 when development > opens. > > Remember to mention the most recent changes in your Changelog entry > (Remove "fp" attribute from *movhf_aarch64 and *movtf_aarch64). gcc/ * config/aarch64/aarch64.md (*movhf_aarch64): Add "movi %0, #0" to zero up register and remove the "fp" attributes. (*movsf_aarch64): Add "movi %0, #0" to zero up register and add the "simd" attributes. (*movdf_aarch64): Likewise. (*movtf_aarch64): Remove the "fp" attributes. OK to commit? Thank you, From b319dead6f72eb36ebedbf27547b2f86f2f9d41f Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 19 Oct 2015 18:31:48 -0500 Subject: [PATCH] [AArch64] Replace insn to zero up SIMD registers gcc/ * config/aarch64/aarch64.md (*movhf_aarch64): Add "movi %0, #0" to zero up register and remove the "fp" attributes. (*movsf_aarch64): Add "movi %0, #0" to zero up register and add the "simd" attributes. (*movdf_aarch64): Likewise. (*movtf_aarch64): Remove the "fp" attributes. --- gcc/config/aarch64/aarch64.md | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f423284..9b282f1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1178,11 +1178,12 @@ ) (define_insn "*movhf_aarch64" - [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r") - (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] + [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w,m,r,m ,r") + (match_operand:HF 1 "general_operand" "Y ,?rY, w,w,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ + movi\\t%0.4h, #0 mov\\t%0.h[0], %w1 umov\\t%w0, %1.h[0] mov\\t%0.h[0], %1.h[0] @@ -1191,18 +1192,18 @@ ldrh\\t%w0, %1 strh\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\ + [(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\ f_loads,f_stores,load1,store1,mov_reg") - (set_attr "simd" "yes,yes,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,yes,yes,*,*,*")] + (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")] ) (define_insn "*movsf_aarch64" - [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ + movi\\t%0.2s, #0 fmov\\t%s0, %w1 fmov\\t%w0, %s1 fmov\\t%s0, %s1 @@ -1212,16 +1213,18 @@ ldr\\t%w0, %1 str\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,load1,store1,mov_reg")] + [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\ + f_loads,f_stores,load1,store1,mov_reg") + (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")] ) (define_insn "*movdf_aarch64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:DF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ + movi\\t%d0, #0 fmov\\t%d0, %x1 fmov\\t%x0, %d1 fmov\\t%d0, %d1 @@ -1231,8 +1234,9 @@ ldr\\t%x0, %1 str\\t%x1, %0 mov\\t%x0, %x1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,load1,store1,mov_reg")] + [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\ + f_loadd,f_stored,load1,store1,mov_reg") + (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")] ) (define_insn "*movtf_aarch64" @@ -1257,7 +1261,6 @@ [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ f_loadd,f_stored,load2,store2,store2") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") - (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*,*") (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] ) -- 2.6.3