From patchwork Wed Mar 9 21:35:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evandro Menezes X-Patchwork-Id: 595240 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E53A0140328 for ; Thu, 10 Mar 2016 08:36:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Y7tGpUCp; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=OROHwgbS4wG7S9g04 RoWBNXSbpkzbuXnz+v/Vbn3MCPHEGI+MmAT5xiM22Ecmv6tF2rcucmB1a8y0J+Rz fC1o93FQoQ7lgWsjMWetA8DrIlO70Bk3QKbYcMFodA+P/2pBua/14pZQdNBmixxV 7WGcpw70up3f0ZPbk9XQgxMA5k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=SYoFCsTOjTVUUNytb9voPtO EJN8=; b=Y7tGpUCpegViikyDkr/jz6nHQmBuoPM1aky7bLfJ0c/BFacB4+FTnns hnm8juMNNBq/OmMi+0c2oaj8w2YKuDcRwXp36uWISx3iErvIwO/pFhVh1zTszywc Cm7+hzK7zx61+A76WxZCYbvc4fGJt2ZtAXrFJQnxUtqo1+IttK6k= Received: (qmail 87523 invoked by alias); 9 Mar 2016 21:36:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 87513 invoked by uid 89); 9 Mar 2016 21:36:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=menezes, evandro, Evandro, Menezes X-HELO: usmailout3.samsung.com Received: from mailout3.w2.samsung.com (HELO usmailout3.samsung.com) (211.189.100.13) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 09 Mar 2016 21:35:54 +0000 Received: from uscpsbgm2.samsung.com (u115.gpu85.samsung.co.kr [203.254.195.115]) by usmailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O3S007MKJZSRR60@usmailout3.samsung.com> for gcc-patches@gcc.gnu.org; Wed, 09 Mar 2016 16:35:52 -0500 (EST) Received: from ussync2.samsung.com ( [203.254.195.82]) by uscpsbgm2.samsung.com (USCPMTA) with SMTP id 6A.3C.07641.83790E65; Wed, 9 Mar 2016 16:35:52 -0500 (EST) Received: from [172.31.207.194] ([105.140.31.10]) by ussync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O3S0025DJZKDD30@ussync2.samsung.com>; Wed, 09 Mar 2016 16:35:52 -0500 (EST) Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register To: Wilco Dijkstra References: <56A94F35.8000000@samsung.com> <56D0D50E.8030802@samsung.com> <56D4D02C.6030309@samsung.com> <56D5E8B6.1090900@samsung.com> Cc: "gcc-patches@gcc.gnu.org" , nd , Marcus Shawcroft , Kyrylo Tkachov , James Greenhalgh From: Evandro Menezes Message-id: <56E0972F.3060207@samsung.com> Date: Wed, 09 Mar 2016 15:35:43 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-version: 1.0 In-reply-to: <56D5E8B6.1090900@samsung.com> Content-type: multipart/mixed; boundary=------------050608000805040604040509 X-IsSubscribed: yes On 03/01/16 13:08, Evandro Menezes wrote: > On 03/01/16 13:02, Wilco Dijkstra wrote: >> Evandro Menezes wrote: >>> The meaning of these attributes are not clear to me. Is there a >>> reference somewhere about which insns are FP or SIMD or neither? >> The meaning should be clear, "fp" is a floating point instruction, >> "simd" a SIMD one >> as defined in ARM-ARM. >> >>> Indeed, I had to add the Y for the f_mcr insn to match it with nosimd. >>> However, I didn't feel that it should be moved to the right, since it's >>> already disparaged. Am I missing something detail? >> It might not matter for this specific case, but I have seen reload >> forcing the very >> first alternative without looking at any costs or preferences - as >> long as it is legal. >> This suggests we need to order alternatives from most preferred >> alternative to least >> preferred one. >> >> I think it is good enough for commit, James? > > Methinks that my issue with those attributes is that I'm not as fluent > in AArch64 as I'd like to be. > > Please, feel free to edit the patch changing the order then. Replace insn to zero up SIMD registers gcc/ * config/aarch64/aarch64.md (*movhf_aarch64): Add "movi %0, #0" to zero up register. (*movsf_aarch64): Likewise and add "simd" and "fp" attributes. (*movdf_aarch64): Likewise. Swapped the order of the constraints to favor MOVI. Just say the word... Thank you, From bcb76a4c864436930e1236e7ce35d9e689adf075 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 19 Oct 2015 18:31:48 -0500 Subject: [PATCH] Replace insn to zero up SIMD registers gcc/ * config/aarch64/aarch64.md (*movhf_aarch64): Add "movi %0, #0" to zero up register. (*movsf_aarch64): Likewise and add "simd" and "fp" attributes. (*movdf_aarch64): Likewise. --- gcc/config/aarch64/aarch64.md | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 68676c9..4502a58 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1163,11 +1163,12 @@ ) (define_insn "*movhf_aarch64" - [(set (match_operand:HF 0 "nonimmediate_operand" "=w, ?r,w,w,m,r,m ,r") - (match_operand:HF 1 "general_operand" "?rY, w,w,m,w,m,rY,r"))] + [(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w,m,r,m ,r") + (match_operand:HF 1 "general_operand" "Y ,?rY, w,w,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], HFmode) || aarch64_reg_or_fp_zero (operands[1], HFmode))" "@ + movi\\t%0.4h, #0 mov\\t%0.h[0], %w1 umov\\t%w0, %1.h[0] mov\\t%0.h[0], %1.h[0] @@ -1176,18 +1177,19 @@ ldrh\\t%w0, %1 strh\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "neon_from_gp,neon_to_gp,neon_move,\ + [(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\ f_loads,f_stores,load1,store1,mov_reg") - (set_attr "simd" "yes,yes,yes,*,*,*,*,*") - (set_attr "fp" "*,*,*,yes,yes,*,*,*")] + (set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*") + (set_attr "fp" "*,*,*,*,yes,yes,*,*,*")] ) (define_insn "*movsf_aarch64" - [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ + movi\\t%0.2s, #0 fmov\\t%s0, %w1 fmov\\t%w0, %s1 fmov\\t%s0, %s1 @@ -1197,16 +1199,19 @@ ldr\\t%w0, %1 str\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,load1,store1,mov_reg")] + [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\ + f_loads,f_stores,load1,store1,mov_reg") + (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*") + (set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*")] ) (define_insn "*movdf_aarch64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") - (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r") + (match_operand:DF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ + movi\\t%d0, #0 fmov\\t%d0, %x1 fmov\\t%x0, %d1 fmov\\t%d0, %d1 @@ -1216,8 +1221,10 @@ ldr\\t%x0, %1 str\\t%x1, %0 mov\\t%x0, %x1" - [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,load1,store1,mov_reg")] + [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\ + f_loadd,f_stored,load1,store1,mov_reg") + (set_attr "simd" "yes,*,*,*,*,*,*,*,*,*") + (set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*")] ) (define_insn "*movtf_aarch64" -- 1.9.1