diff mbox

[rs6000] Fix type attribute for a few insns

Message ID 56B409F8.6080600@linux.vnet.ibm.com
State New
Headers show

Commit Message

Pat Haugen Feb. 5, 2016, 2:33 a.m. UTC 
The following patch fixes a few insns that were specifying an incorrect 
'type' attribute.

Bootstrap/regtest on powerpc64-linux with no new regressions. Ok for trunk?

-Pat


2016-02-04  Pat Haugen  <pthaugen@us.ibm.com>

         * config/rs6000/crypto.md (crypto_vpermxor_<mode>): Correct 
insn type.
         * config/rs6000/rs6000.md (mov<mode>_hardfloat): Likewise.
         (*ieee128_mfvsrd_64bit): Likewise.
         (*ieee128_mfvsrd_32bit): Likewise.

Comments

David Edelsohn Feb. 5, 2016, 2:47 a.m. UTC | #1 
On Thu, Feb 4, 2016 at 9:33 PM, Pat Haugen <pthaugen@linux.vnet.ibm.com> wrote:
> The following patch fixes a few insns that were specifying an incorrect
> 'type' attribute.
>
> Bootstrap/regtest on powerpc64-linux with no new regressions. Ok for trunk?
>
> -Pat
>
>
> 2016-02-04  Pat Haugen  <pthaugen@us.ibm.com>
>
>         * config/rs6000/crypto.md (crypto_vpermxor_<mode>): Correct insn
> type.
>         * config/rs6000/rs6000.md (mov<mode>_hardfloat): Likewise.
>         (*ieee128_mfvsrd_64bit): Likewise.
>         (*ieee128_mfvsrd_32bit): Likewise.

Okay.

Thanks, David
diff mbox

Patch

Index: config/rs6000/crypto.md
===================================================================
--- config/rs6000/crypto.md	(revision 232743)
+++ config/rs6000/crypto.md	(working copy)
@@ -87,7 +87,7 @@  (define_insn "crypto_vpermxor_<mode>"
 			UNSPEC_VPERMXOR))]
   "TARGET_P8_VECTOR"
   "vpermxor %0,%1,%2,%3"
-  [(set_attr "type" "crypto")])
+  [(set_attr "type" "vecperm")])
 
 ;; 1 operand crypto instruction
 (define_insn "crypto_vsbox"
Index: config/rs6000/rs6000.md
===================================================================
--- config/rs6000/rs6000.md	(revision 232743)
+++ config/rs6000/rs6000.md	(working copy)
@@ -6521,7 +6522,7 @@  (define_insn "mov<mode>_hardfloat"
    mt%0 %1
    mf%1 %0
    nop"
-  [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*")
+  [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
    (set_attr "length" "4")])
 
 (define_insn "*mov<mode>_softfloat"
@@ -13520,7 +13521,7 @@  (define_insn "*ieee128_mfvsrd_64bit"
    mfvsrd %0,%x1
    stxsdx %x1,%y0
    xxlor %x0,%x1,%x1"
-  [(set_attr "type" "mftgpr,vecsimple,fpstore")])
+  [(set_attr "type" "mftgpr,fpstore,vecsimple")])
 
 
 (define_insn "*ieee128_mfvsrd_32bit"
@@ -13531,7 +13532,7 @@  (define_insn "*ieee128_mfvsrd_32bit"
   "@
    stxsdx %x1,%y0
    xxlor %x0,%x1,%x1"
-  [(set_attr "type" "vecsimple,fpstore")])
+  [(set_attr "type" "fpstore,vecsimple")])
 
 (define_insn "*ieee128_mfvsrwz"
   [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z")