diff mbox

[AARCH64,ACLE,NEON] Implement vcvt*_s64_f64 and vcvt*_u64_f64 NEON intrinsics.

Message ID 56968CFE.8010805@foss.arm.com
State New
Headers show

Commit Message

Bilyan Borisov Jan. 13, 2016, 5:44 p.m. UTC 
This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector
intrinsics, where R is ['',a,m,n,p]. Since these intrinsics are
identical in semantics to the corresponding scalar variants, they are
implemented in terms of them, with appropriate packing and unpacking
of vector arguments. New test cases, covering all the intrinsics were
also added.

Cross tested on aarch64-none-elf and aarch64-none-linux-gnu. 
Bootstrapped and
tested on aarch64-none-linux-gnu.

---

gcc/

2015-XX-XX  Bilyan Borisov  <bilyan.borisov@arm.com>

	* config/aarch64/arm_neon.h (vcvt_s64_f64): New intrinsic.
	(vcvt_u64_f64): Likewise.
	(vcvta_s64_f64): Likewise.
	(vcvta_u64_f64): Likewise.
	(vcvtm_s64_f64): Likewise.
	(vcvtm_u64_f64): Likewise.
	(vcvtn_s64_f64): Likewise.
	(vcvtn_u64_f64): Likewise.
	(vcvtp_s64_f64): Likewise.
	(vcvtp_u64_f64): Likewise.

gcc/testsuite/

2015-XX-XX  Bilyan Borisov  <bilyan.borisov@arm.com>

	* gcc.target/aarch64/simd/vcvt_s64_f64_1.c: New.
	* gcc.target/aarch64/simd/vcvt_u64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvta_s64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvta_u64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvtm_s64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvtm_u64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvtn_s64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvtn_u64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvtp_s64_f64_1.c: Likewise.
	* gcc.target/aarch64/simd/vcvtp_u64_f64_1.c: Likewise.

Comments

James Greenhalgh Jan. 21, 2016, 12:32 p.m. UTC | #1 
On Wed, Jan 13, 2016 at 05:44:30PM +0000, Bilyan Borisov wrote:
> This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector
> intrinsics, where R is ['',a,m,n,p]. Since these intrinsics are
> identical in semantics to the corresponding scalar variants, they are
> implemented in terms of them, with appropriate packing and unpacking
> of vector arguments. New test cases, covering all the intrinsics were
> also added.

This patch is very low risk, gets us another step towards closing pr58693,
and was posted before the Stage 3 deadline. This is OK for trunk.

Thanks,
James

> 
> Cross tested on aarch64-none-elf and aarch64-none-linux-gnu.
> Bootstrapped and
> tested on aarch64-none-linux-gnu.
> 
> ---
> 
> gcc/
> 
> 2015-XX-XX  Bilyan Borisov  <bilyan.borisov@arm.com>
> 
> 	* config/aarch64/arm_neon.h (vcvt_s64_f64): New intrinsic.
> 	(vcvt_u64_f64): Likewise.
> 	(vcvta_s64_f64): Likewise.
> 	(vcvta_u64_f64): Likewise.
> 	(vcvtm_s64_f64): Likewise.
> 	(vcvtm_u64_f64): Likewise.
> 	(vcvtn_s64_f64): Likewise.
> 	(vcvtn_u64_f64): Likewise.
> 	(vcvtp_s64_f64): Likewise.
> 	(vcvtp_u64_f64): Likewise.
> 
> gcc/testsuite/
> 
> 2015-XX-XX  Bilyan Borisov  <bilyan.borisov@arm.com>
> 
> 	* gcc.target/aarch64/simd/vcvt_s64_f64_1.c: New.
> 	* gcc.target/aarch64/simd/vcvt_u64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvta_s64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvta_u64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvtm_s64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvtm_u64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvtn_s64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvtn_u64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvtp_s64_f64_1.c: Likewise.
> 	* gcc.target/aarch64/simd/vcvtp_u64_f64_1.c: Likewise.
James Greenhalgh Jan. 25, 2016, 11:43 a.m. UTC | #2 
On Thu, Jan 21, 2016 at 12:32:07PM +0000, James Greenhalgh wrote:
> On Wed, Jan 13, 2016 at 05:44:30PM +0000, Bilyan Borisov wrote:
> > This patch implements all the vcvtR_s64_f64 and vcvtR_u64_f64 vector
> > intrinsics, where R is ['',a,m,n,p]. Since these intrinsics are
> > identical in semantics to the corresponding scalar variants, they are
> > implemented in terms of them, with appropriate packing and unpacking
> > of vector arguments. New test cases, covering all the intrinsics were
> > also added.
> 
> This patch is very low risk, gets us another step towards closing pr58693,
> and was posted before the Stage 3 deadline. This is OK for trunk.

I realised you don't have commit access, so I've committed this on your
behalf as revision 232789.

Thanks,
James

> > gcc/
> > 
> > 2015-XX-XX  Bilyan Borisov  <bilyan.borisov@arm.com>
> > 
> > 	* config/aarch64/arm_neon.h (vcvt_s64_f64): New intrinsic.
> > 	(vcvt_u64_f64): Likewise.
> > 	(vcvta_s64_f64): Likewise.
> > 	(vcvta_u64_f64): Likewise.
> > 	(vcvtm_s64_f64): Likewise.
> > 	(vcvtm_u64_f64): Likewise.
> > 	(vcvtn_s64_f64): Likewise.
> > 	(vcvtn_u64_f64): Likewise.
> > 	(vcvtp_s64_f64): Likewise.
> > 	(vcvtp_u64_f64): Likewise.
> > 
> > gcc/testsuite/
> > 
> > 2015-XX-XX  Bilyan Borisov  <bilyan.borisov@arm.com>
> > 
> > 	* gcc.target/aarch64/simd/vcvt_s64_f64_1.c: New.
> > 	* gcc.target/aarch64/simd/vcvt_u64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvta_s64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvta_u64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvtm_s64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvtm_u64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvtn_s64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvtn_u64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvtp_s64_f64_1.c: Likewise.
> > 	* gcc.target/aarch64/simd/vcvtp_u64_f64_1.c: Likewise.
>
diff mbox

Patch

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index c78f2524fa62b1ceedce86ee64cadfa67d3b0d0c..1e19a9e2ed96b7b7c5715be41b98e9c1407a74f9 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -13218,6 +13218,18 @@  vcvtq_u32_f32 (float32x4_t __a)
   return __builtin_aarch64_lbtruncuv4sfv4si_us (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvt_s64_f64 (float64x1_t __a)
+{
+  return (int64x1_t) {vcvtd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvt_u64_f64 (float64x1_t __a)
+{
+  return (uint64x1_t) {vcvtd_u64_f64 (__a[0])};
+}
+
 __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
 vcvtq_s64_f64 (float64x2_t __a)
 {
@@ -13280,6 +13292,18 @@  vcvtaq_u32_f32 (float32x4_t __a)
   return __builtin_aarch64_lrounduv4sfv4si_us (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvta_s64_f64 (float64x1_t __a)
+{
+  return (int64x1_t) {vcvtad_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvta_u64_f64 (float64x1_t __a)
+{
+  return (uint64x1_t) {vcvtad_u64_f64 (__a[0])};
+}
+
 __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
 vcvtaq_s64_f64 (float64x2_t __a)
 {
@@ -13342,6 +13366,18 @@  vcvtmq_u32_f32 (float32x4_t __a)
   return __builtin_aarch64_lflooruv4sfv4si_us (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvtm_s64_f64 (float64x1_t __a)
+{
+  return (int64x1_t) {vcvtmd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvtm_u64_f64 (float64x1_t __a)
+{
+  return (uint64x1_t) {vcvtmd_u64_f64 (__a[0])};
+}
+
 __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
 vcvtmq_s64_f64 (float64x2_t __a)
 {
@@ -13404,6 +13440,18 @@  vcvtnq_u32_f32 (float32x4_t __a)
   return __builtin_aarch64_lfrintnuv4sfv4si_us (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvtn_s64_f64 (float64x1_t __a)
+{
+  return (int64x1_t) {vcvtnd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvtn_u64_f64 (float64x1_t __a)
+{
+  return (uint64x1_t) {vcvtnd_u64_f64 (__a[0])};
+}
+
 __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
 vcvtnq_s64_f64 (float64x2_t __a)
 {
@@ -13466,6 +13514,18 @@  vcvtpq_u32_f32 (float32x4_t __a)
   return __builtin_aarch64_lceiluv4sfv4si_us (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvtp_s64_f64 (float64x1_t __a)
+{
+  return (int64x1_t) {vcvtpd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvtp_u64_f64 (float64x1_t __a)
+{
+  return (uint64x1_t) {vcvtpd_u64_f64 (__a[0])};
+}
+
 __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
 vcvtpq_s64_f64 (float64x2_t __a)
 {
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvt_s64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvt_s64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..02f59fc7e58c988141f8f00c8866c71f2d5d660b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvt_s64_f64_1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  int64x1_t b1 = vcvt_s64_f64 (a);
+
+  if (b1[0] != 0)
+    abort ();
+
+  volatile float64x1_t a2 = {-0.5};
+  int64x1_t b2 = vcvt_s64_f64 (a2);
+
+  if (b2[0] != 0)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtzs\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvt_u64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvt_u64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..089cc793a372b20f7657a9aa9742f3f335149fb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvt_u64_f64_1.c
@@ -0,0 +1,19 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  uint64x1_t b1 = vcvt_u64_f64 (a);
+
+  if (b1[0] != 0)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtzu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvta_s64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvta_s64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..d5cd5bb77360b3470746539cd586edf80e8879b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvta_s64_f64_1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  int64x1_t b1 = vcvta_s64_f64 (a);
+
+  if (b1[0] != 1)
+    abort ();
+
+  volatile float64x1_t a2 = {-0.5};
+  int64x1_t b2 = vcvta_s64_f64 (a2);
+
+  if (b2[0] != -1)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtas\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvta_u64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvta_u64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..aaddfa0604c33b947d3c79d538b295d08b54124c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvta_u64_f64_1.c
@@ -0,0 +1,19 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  uint64x1_t b1 = vcvta_u64_f64 (a);
+
+  if (b1[0] != 1)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtau\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvtm_s64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvtm_s64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..a24b737dc3fd46fea2c04b32a53e544914a53a6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvtm_s64_f64_1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  int64x1_t b1 = vcvtm_s64_f64 (a);
+
+  if (b1[0] != 0)
+    abort ();
+
+  volatile float64x1_t a2 = {-0.5};
+  int64x1_t b2 = vcvtm_s64_f64 (a2);
+
+  if (b2[0] != -1)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtms\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvtm_u64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvtm_u64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0f2751cf29bc6a9c81ed760a014e525f52ade730
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvtm_u64_f64_1.c
@@ -0,0 +1,19 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  uint64x1_t b1 = vcvtm_u64_f64 (a);
+
+  if (b1[0] != 0)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtmu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvtn_s64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvtn_s64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..4a312db906a1bc4cac29abc136e7123a54300865
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvtn_s64_f64_1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  int64x1_t b1 = vcvtn_s64_f64 (a);
+
+  if (b1[0] != 0)
+    abort ();
+
+  volatile float64x1_t a2 = {-0.5};
+  int64x1_t b2 = vcvtn_s64_f64 (a2);
+
+  if (b2[0] != 0)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtns\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvtn_u64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvtn_u64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..823834c72ef656c86d208ef0d534e1aa8c7290a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvtn_u64_f64_1.c
@@ -0,0 +1,19 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  uint64x1_t b1 = vcvtn_u64_f64 (a);
+
+  if (b1[0] != 0)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtnu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvtp_s64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvtp_s64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ff80e292c973f27b66b81d3ffa12d76b4402dcb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvtp_s64_f64_1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  int64x1_t b1 = vcvtp_s64_f64 (a);
+
+  if (b1[0] != 1)
+    abort ();
+
+  volatile float64x1_t a2 = {-0.5};
+  int64x1_t b2 = vcvtp_s64_f64 (a2);
+
+  if (b2[0] != 0)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtps\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vcvtp_u64_f64_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vcvtp_u64_f64_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..6346ce5e6b3cc78911a86e422a0a0fa741c1dbb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vcvtp_u64_f64_1.c
@@ -0,0 +1,19 @@ 
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+  volatile float64x1_t a = {0.5};
+  uint64x1_t b1 = vcvtp_u64_f64 (a);
+
+  if (b1[0] != 1)
+    abort ();
+
+  return 0;
+}
+/* { dg-final { scan-assembler "fcvtpu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */