From patchwork Mon Jan 11 16:41:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 566032 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7C0751402D9 for ; Tue, 12 Jan 2016 03:41:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=brc4Fux3; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=NCkeDnuKkOIrr8So2gQ5+k/q/BJhUlUiQjQxx9tl+ga QApgbp0VuEn+Ud2IJSgtZXqTbnE/SQ1sKHocLBQUXzRcxfqvQwKrFz7N73Pu4b+V 6j6Ysra6q88EagPduVG0opN4/CEtj11GLW4sQV2m9xf8uaYSB0h2sF7W6rF+m6Ws = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=j6+1L0Tbm05o/z8J6J53ZX52UpI=; b=brc4Fux3w9R40n/2y j/c+L+YlDB67REW7onEHM9EER03u59cfpuC0AWVSOeUUyip+PS5VcRbx270t90SO Yl+vUFNT5DgYgweKkNcPsLuLGRWar7aIa2w6sVbr+WXSWfotF/2ypI06uBO967s5 YIjpfSdgKfMaWxHc8IF1xxpnG4= Received: (qmail 30073 invoked by alias); 11 Jan 2016 16:41:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30055 invoked by uid 89); 11 Jan 2016 16:41:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.4 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=followed, ZERO_EXTRACT, neg, aforementioned X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Jan 2016 16:41:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B5A674AE; Mon, 11 Jan 2016 08:40:51 -0800 (PST) Received: from [10.2.206.200] (e100706-lin.cambridge.arm.com [10.2.206.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AE5173F24D; Mon, 11 Jan 2016 08:41:25 -0800 (PST) Message-ID: <5693DB32.3010106@foss.arm.com> Date: Mon, 11 Jan 2016 16:41:22 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] Handle compare of zero_extract form of TST-immediate in rtx costs Hi all, The test gcc.target/aarch64/tst_3.c fails for an explicit -mcpu=cortex-a53 because we don't handle the recent compare with zero_extract pattern properly in rtx costs, so we end up recursing into its operands and end up rejecting the combination for some CPUs, generating an AND-immediate followed by a comparison against zero, instead of the TST-immediate instruction expected by the test. This patch adds handling for that pattern so that we properly handle it the same ways as an ANDS instruction. With this patch the aforementioned test passes for -mcpu=cortex-a53 as well. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for trunk? Thanks, Kyrill 2016-01-11 Kyrylo Tkachov * config/aarch64/aarch64.c (aarch64_rtx_costs, COMPARE case): Handle COMPARE of ZERO_EXTRACT against zero form of TST-immediate. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index a66508a11fe380e9277d1589ce9dc11eef2fe6a3..8fe433f8f1dac836983d57d5c3dde128697dc2d8 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -6490,6 +6490,23 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED, goto cost_minus; } + if (GET_CODE (op0) == ZERO_EXTRACT && op1 == const0_rtx + && GET_MODE (x) == CC_NZmode && CONST_INT_P (XEXP (op0, 1)) + && CONST_INT_P (XEXP (op0, 2))) + { + /* COMPARE of ZERO_EXTRACT form of TST-immediate. + Handle it here directly rather than going to cost_logic + since we know the immediate generated for the TST is valid + so we can avoid creating an intermediate rtx for it only + for costing purposes. */ + if (speed) + *cost += extra_cost->alu.logical; + + *cost += rtx_cost (XEXP (op0, 0), GET_MODE (op0), + ZERO_EXTRACT, 0, speed); + return true; + } + if (GET_CODE (op1) == NEG) { /* CMN. */