RFD: annotate iterator patterns with expanded forms

Message ID	565DB94D.1050106@redhat.com
State	New
Headers	show Return-Path: <gcc-patches-return-415933-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=eQiMH7yF0L9fceO7QfYlZDDdXLCQHh4xhArmU5jp6f1PYXIP64 ZlCaOjpVoUTMRAqhYzQePUw0s3krGS7X2XvuP99aW/8OmGV0Ro4/tamukQth6S/6 n/hXX0OWszPiz3jdb/YXaLyaEEYvEzvB7VaQTuHcVnKTv/ERcE/pi2W6E= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org To: GCC Patches <gcc-patches@gcc.gnu.org> Cc: Uros Bizjak <ubizjak@gmail.com> From: Bernd Schmidt <bschmidt@redhat.com> Subject: RFD: annotate iterator patterns with expanded forms Message-ID: <565DB94D.1050106@redhat.com> Date: Tue, 1 Dec 2015 16:14:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------060102010707040704090901"

diff --git a/gcc/gensupport.c b/gcc/gensupport.c index 484ead2..4daaef9 100644 --- a/gcc/gensupport.c +++ b/gcc/gensupport.c @@ -2236,6 +2236,32 @@ rtx_handle_directive (file_location loc, const char *rtx_name) rtx x; unsigned int i; + if (subrtxs.length () > 1 + && (GET_CODE (subrtxs[0]) == DEFINE_INSN + || GET_CODE (subrtxs[0]) == DEFINE_EXPAND)) + { + const char *p = ""; + fprintf (stderr, "%s:%d\\ni\\n;; Expands to:\\n;; ", loc.filename, loc.lineno); + int len = 3; + int p_len = 0; + FOR_EACH_VEC_ELT (subrtxs, i, x) + { + int this_len = strlen (XSTR (x, 0)); + if (len + this_len + p_len >= 78) + { + fprintf (stderr, "\\n;; "); + len = 3; + p = ""; + p_len = 0; + } + fprintf (stderr, "%s%s", p, XSTR (x, 0)); + len += this_len + p_len; + p = ", "; + p_len = 2; + } + fprintf (stderr, "\\n.\n"); + } + FOR_EACH_VEC_ELT (subrtxs, i, x) process_rtx (x, loc); } --- ../../git/gcc/config/i386/i386.md 2015-11-30 14:34:27.995459571 +0100 +++ ./i386.md 2015-12-01 15:58:59.817779596 +0100 @@ -1199,6 +1199,8 @@ ;; Compare and branch/compare and store instructions. +;; Expands to: +;; cbranchqi4, cbranchhi4, cbranchsi4, cbranchdi4, cbranchti4 (define_expand "cbranch<mode>4" [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand") @@ -1217,6 +1219,8 @@ DONE; }) +;; Expands to: +;; cstoreqi4, cstorehi4, cstoresi4, cstoredi4 (define_expand "cstore<mode>4" [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SWIM 2 "nonimmediate_operand") @@ -1233,11 +1237,15 @@ DONE; }) +;; Expands to: +;; cmpsi_1, cmpdi_1 (define_expand "cmp<mode>_1" [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SWI48 0 "nonimmediate_operand") (match_operand:SWI48 1 "<general_operand>")))]) +;; Expands to: +;; *cmpqi_ccno_1, *cmphi_ccno_1, *cmpsi_ccno_1, *cmpdi_ccno_1 (define_insn "*cmp<mode>_ccno_1" [(set (reg FLAGS_REG) (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>") @@ -1251,6 +1259,8 @@ (set_attr "modrm_class" "op0,unknown") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *cmpqi_1, *cmphi_1, *cmpsi_1, *cmpdi_1 (define_insn "*cmp<mode>_1" [(set (reg FLAGS_REG) (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>") @@ -1260,6 +1270,8 @@ [(set_attr "type" "icmp") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *cmpqi_minus_1, *cmphi_minus_1, *cmpsi_minus_1, *cmpdi_minus_1 (define_insn "*cmp<mode>_minus_1" [(set (reg FLAGS_REG) (compare @@ -1382,6 +1394,8 @@ DONE; }) +;; Expands to: +;; cbranchsf4, cbranchdf4 (define_expand "cbranch<mode>4" [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand") @@ -1399,6 +1413,8 @@ DONE; }) +;; Expands to: +;; cstoresf4, cstoredf4 (define_expand "cstore<mode>4" [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand") @@ -1450,6 +1466,8 @@ ;; We may not use "#" to split and emit these, since the REG_DEAD notes ;; used to manage the reg stack popping would not be preserved. +;; Expands to: +;; *cmpsf_0_i387, *cmpdf_0_i387, *cmpxf_0_i387 (define_insn "*cmp<mode>_0_i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -1516,6 +1534,8 @@ (set_attr "unit" "i387") (set_attr "mode" "XF")]) +;; Expands to: +;; *cmpsf_i387, *cmpdf_i387 (define_insn "*cmp<mode>_i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -1549,6 +1569,8 @@ (set_attr "unit" "i387") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *cmpusf_i387, *cmpudf_i387, *cmpuxf_i387 (define_insn "*cmpu<mode>_i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -1582,6 +1604,9 @@ (set_attr "unit" "i387") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *cmpsf_hi_i387, *cmpdf_hi_i387, *cmpxf_hi_i387, *cmpsf_si_i387 +;; *cmpdf_si_i387, *cmpxf_si_i387 (define_insn "*cmp<X87MODEF:mode>_<SWI24:mode>_i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -1666,6 +1691,8 @@ (define_mode_iterator FPCMP [CCFP CCFPU]) (define_mode_attr unord [(CCFP "") (CCFPU "u")]) +;; Expands to: +;; *cmpisf_mixed, *cmpidf_mixed, *cmpiusf_mixed, *cmpiudf_mixed (define_insn "*cmpi<FPCMP:unord><MODEF:mode>_mixed" [(set (reg:FPCMP FLAGS_REG) (compare:FPCMP @@ -1695,6 +1722,9 @@ ] (symbol_ref "true")))]) +;; Expands to: +;; *cmpisf_i387, *cmpidf_i387, *cmpixf_i387, *cmpiusf_i387, *cmpiudf_i387 +;; *cmpiuxf_i387 (define_insn "*cmpi<FPCMP:unord><X87MODEF:mode>_i387" [(set (reg:FPCMP FLAGS_REG) (compare:FPCMP @@ -1713,6 +1743,8 @@ ;; Push/pop instructions. +;; Expands to: +;; *pushdi2, *pushti2 (define_insn "*push<mode>2" [(set (match_operand:DWI 0 "push_operand" "=<") (match_operand:DWI 1 "general_no_elim_operand" "riF*o"))] @@ -1808,6 +1840,8 @@ ;; of rounding the amount pushed up to a word. ;; For TARGET_64BIT we always round up to 8 bytes. +;; Expands to: +;; *pushqi2_rex64, *pushhi2_rex64, *pushsi2_rex64 (define_insn "*push<mode>2_rex64" [(set (match_operand:SWI124 0 "push_operand" "=X") (match_operand:SWI124 1 "nonmemory_no_elim_operand" "r"))] @@ -1816,6 +1850,8 @@ [(set_attr "type" "push") (set_attr "mode" "DI")]) +;; Expands to: +;; *pushqi2, *pushhi2 (define_insn "*push<mode>2" [(set (match_operand:SWI12 0 "push_operand" "=X") (match_operand:SWI12 1 "nonmemory_no_elim_operand" "rn"))] @@ -1824,6 +1860,8 @@ [(set_attr "type" "push") (set_attr "mode" "SI")]) +;; Expands to: +;; *pushsi2_prologue, *pushdi2_prologue (define_insn "*push<mode>2_prologue" [(set (match_operand:W 0 "push_operand" "=<") (match_operand:W 1 "general_no_elim_operand" "r*m")) @@ -1833,6 +1871,8 @@ [(set_attr "type" "push") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *popsi1, *popdi1 (define_insn "*pop<mode>1" [(set (match_operand:W 0 "nonimmediate_operand" "=r*m") (match_operand:W 1 "pop_operand" ">"))] @@ -1841,6 +1881,8 @@ [(set_attr "type" "pop") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *popsi1_epilogue, *popdi1_epilogue (define_insn "*pop<mode>1_epilogue" [(set (match_operand:W 0 "nonimmediate_operand" "=r*m") (match_operand:W 1 "pop_operand" ">")) @@ -1850,6 +1892,8 @@ [(set_attr "type" "pop") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *pushflsi2, *pushfldi2 (define_insn "*pushfl<mode>2" [(set (match_operand:W 0 "push_operand" "=<") (match_operand:W 1 "flags_reg_operand"))] @@ -1858,6 +1902,8 @@ [(set_attr "type" "push") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *popflsi1, *popfldi1 (define_insn "*popfl<mode>1" [(set (match_operand:W 0 "flags_reg_operand") (match_operand:W 1 "pop_operand" ">"))] @@ -1943,12 +1989,16 @@ DONE; }) +;; Expands to: +;; movqi, movhi, movsi, movdi (define_expand "mov<mode>" [(set (match_operand:SWI1248x 0 "nonimmediate_operand") (match_operand:SWI1248x 1 "general_operand"))] "" "ix86_expand_move (<MODE>mode, operands); DONE;") +;; Expands to: +;; *movsi_xor, *movdi_xor (define_insn "*mov<mode>_xor" [(set (match_operand:SWI48 0 "register_operand" "=r") (match_operand:SWI48 1 "const0_operand")) @@ -1960,6 +2010,8 @@ (set_attr "mode" "SI") (set_attr "length_immediate" "0")]) +;; Expands to: +;; *movsi_or, *movdi_or (define_insn "*mov<mode>_or" [(set (match_operand:SWI48 0 "register_operand" "=r") (match_operand:SWI48 1 "const_int_operand")) @@ -2606,6 +2658,8 @@ ;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available +;; Expands to: +;; *movabsqi_1, *movabshi_1, *movabssi_1, *movabsdi_1 (define_insn "*movabs<mode>_1" [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) (match_operand:SWI1248x 1 "nonmemory_operand" "a,r"))] @@ -2630,6 +2684,8 @@ (set_attr "memory" "store") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *movabsqi_2, *movabshi_2, *movabssi_2, *movabsdi_2 (define_insn "*movabs<mode>_2" [(set (match_operand:SWI1248x 0 "register_operand" "=a,r") (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] @@ -2654,6 +2710,8 @@ (set_attr "memory" "load") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *swapsi, *swapdi (define_insn "*swap<mode>" [(set (match_operand:SWI48 0 "register_operand" "+r") (match_operand:SWI48 1 "register_operand" "+r")) @@ -2668,6 +2726,8 @@ (set_attr "amdfam10_decode" "double") (set_attr "bdver1_decode" "double")]) +;; Expands to: +;; *swapqi_1, *swaphi_1 (define_insn "*swap<mode>_1" [(set (match_operand:SWI12 0 "register_operand" "+r") (match_operand:SWI12 1 "register_operand" "+r")) @@ -2684,6 +2744,8 @@ ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL ;; is disabled for AMDFAM10 +;; Expands to: +;; *swapqi_2, *swaphi_2 (define_insn "*swap<mode>_2" [(set (match_operand:SWI12 0 "register_operand" "+<r>") (match_operand:SWI12 1 "register_operand" "+<r>")) @@ -2696,6 +2758,8 @@ (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector")]) +;; Expands to: +;; movstrictqi, movstricthi (define_expand "movstrict<mode>" [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand")) (match_operand:SWI12 1 "general_operand"))] @@ -2711,6 +2775,8 @@ operands[1] = force_reg (<MODE>mode, operands[1]); }) +;; Expands to: +;; *movstrictqi_1, *movstricthi_1 (define_insn "*movstrict<mode>_1" [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" "+<r>m,<r>")) @@ -2721,6 +2787,8 @@ [(set_attr "type" "imov") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *movstrictqi_xor, *movstricthi_xor (define_insn "*movstrict<mode>_xor" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>")) (match_operand:SWI12 1 "const0_operand")) @@ -2732,6 +2800,8 @@ (set_attr "mode" "<MODE>") (set_attr "length_immediate" "0")]) +;; Expands to: +;; extvhi, extvsi (define_expand "extv<mode>" [(set (match_operand:SWI24 0 "register_operand") (sign_extract:SWI24 (match_operand:SWI24 1 "register_operand") @@ -2747,6 +2817,8 @@ operands[1] = copy_to_reg (operands[1]); }) +;; Expands to: +;; *extvhi, *extvsi (define_insn "*extv<mode>" [(set (match_operand:SWI24 0 "register_operand" "=R") (sign_extract:SWI24 (match_operand 1 "ext_register_operand" "Q") @@ -2784,6 +2856,8 @@ (const_string "SI") (const_string "QI")))]) +;; Expands to: +;; extzvhi, extzvsi, extzvdi (define_expand "extzv<mode>" [(set (match_operand:SWI248 0 "register_operand") (zero_extract:SWI248 (match_operand:SWI248 1 "register_operand") @@ -2802,6 +2876,8 @@ operands[1] = copy_to_reg (operands[1]); }) +;; Expands to: +;; *extzvhi, *extzvsi, *extzvdi (define_insn "*extzv<mode>" [(set (match_operand:SWI248 0 "register_operand" "=R") (zero_extract:SWI248 (match_operand 1 "ext_register_operand" "Q") @@ -2840,6 +2916,8 @@ (const_string "SI") (const_string "QI")))]) +;; Expands to: +;; insvhi, insvsi, insvdi (define_expand "insv<mode>" [(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand") (match_operand:SI 1 "const_int_operand") @@ -2870,6 +2948,8 @@ DONE; }) +;; Expands to: +;; insvhi_1, insvsi_1, insvdi_1 (define_insn "insv<mode>_1" [(set (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "+Q,Q") (const_int 8) @@ -3072,6 +3152,8 @@ "TARGET_64BIT || TARGET_SSE" "ix86_expand_move (TFmode, operands); DONE;") +;; Expands to: +;; movsf, movdf, movxf (define_expand "mov<mode>" [(set (match_operand:X87MODEF 0 "nonimmediate_operand") (match_operand:X87MODEF 1 "general_operand"))] @@ -3637,6 +3719,8 @@ [(set_attr "type" "fxch") (set_attr "mode" "XF")]) +;; Expands to: +;; *swapsf, *swapdf (define_insn "*swap<mode>" [(set (match_operand:MODEF 0 "fp_register_operand" "+f") (match_operand:MODEF 1 "fp_register_operand" "+f")) @@ -3765,6 +3849,8 @@ (set (match_dup 4) (const_int 0))] "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") +;; Expands to: +;; zero_extendqidi2, zero_extendhidi2 (define_insn "zero_extend<mode>di2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI @@ -3774,6 +3860,8 @@ [(set_attr "type" "imovx") (set_attr "mode" "SI")]) +;; Expands to: +;; zero_extendqisi2, zero_extendhisi2 (define_expand "zero_extend<mode>si2" [(set (match_operand:SI 0 "register_operand") (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand")))] @@ -3813,6 +3901,8 @@ [(set_attr "type" "alu1") (set_attr "mode" "SI")]) +;; Expands to: +;; *zero_extendqisi2, *zero_extendhisi2 (define_insn "*zero_extend<mode>si2" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI @@ -4022,6 +4112,8 @@ DONE; }) +;; Expands to: +;; extendqidi2, extendhidi2 (define_insn "extend<mode>di2" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI @@ -4269,6 +4361,8 @@ [(set_attr "type" "fmov") (set_attr "mode" "SF,XF")]) +;; Expands to: +;; extendsfxf2, extenddfxf2 (define_expand "extend<mode>xf2" [(set (match_operand:XF 0 "nonimmediate_operand") (float_extend:XF (match_operand:MODEF 1 "general_operand")))] @@ -4289,6 +4383,8 @@ } }) +;; Expands to: +;; *extendsfxf2_i387, *extenddfxf2_i387 (define_insn "*extend<mode>xf2_i387" [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") (float_extend:XF @@ -4493,6 +4589,8 @@ ;; Conversion from XFmode to {SF,DF}mode +;; Expands to: +;; truncxfsf2, truncxfdf2 (define_expand "truncxf<mode>2" [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand") (float_truncate:MODEF @@ -4541,6 +4639,8 @@ (set_attr "unit" "*,i387,i387,i387") (set_attr "mode" "DF")]) +;; Expands to: +;; truncxfsf2_i387_noop, truncxfdf2_i387_noop (define_insn "truncxf<mode>2_i387_noop" [(set (match_operand:MODEF 0 "register_operand" "=f") (float_truncate:MODEF @@ -4550,6 +4650,8 @@ [(set_attr "type" "fmov") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *truncxfsf2_i387, *truncxfdf2_i387 (define_insn "*truncxf<mode>2_i387" [(set (match_operand:MODEF 0 "memory_operand" "=m") (float_truncate:MODEF @@ -4591,6 +4693,8 @@ } }) +;; Expands to: +;; fix_truncsfdi2, fix_truncdfdi2 (define_expand "fix_trunc<mode>di2" [(parallel [(set (match_operand:DI 0 "nonimmediate_operand") (fix:DI (match_operand:MODEF 1 "register_operand"))) @@ -4628,6 +4732,8 @@ } }) +;; Expands to: +;; fix_truncsfsi2, fix_truncdfsi2 (define_expand "fix_trunc<mode>si2" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand") (fix:SI (match_operand:MODEF 1 "register_operand"))) @@ -4652,6 +4758,8 @@ ;; Signed conversion to HImode. +;; Expands to: +;; fix_truncsfhi2, fix_truncdfhi2, fix_truncxfhi2 (define_expand "fix_trunc<mode>hi2" [(parallel [(set (match_operand:HI 0 "nonimmediate_operand") (fix:HI (match_operand:X87MODEF 1 "register_operand"))) @@ -4668,6 +4776,8 @@ ;; Unsigned conversion to SImode. +;; Expands to: +;; fixuns_truncsfsi2, fixuns_truncdfsi2 (define_expand "fixuns_trunc<mode>si2" [(parallel [(set (match_operand:SI 0 "register_operand") @@ -4713,6 +4823,8 @@ ;; Without these patterns, we'll try the unsigned SI conversion which ;; is complex for SSE, rather than the signed SI conversion, which isn't. +;; Expands to: +;; fixuns_truncsfhi2, fixuns_truncdfhi2 (define_expand "fixuns_trunc<mode>hi2" [(set (match_dup 2) (fix:SI (match_operand:MODEF 1 "nonimmediate_operand"))) @@ -4722,6 +4834,8 @@ "operands[2] = gen_reg_rtx (SImode);") ;; When SSE is available, it is always faster to use it! +;; Expands to: +;; fix_truncsfsi_sse, fix_truncsfdi_sse, fix_truncdfsi_sse, fix_truncdfdi_sse (define_insn "fix_trunc<MODEF:mode><SWI48:mode>_sse" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (fix:SWI48 (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))] @@ -4778,6 +4892,8 @@ [(set_attr "type" "fisttp") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fix_trunchi_i387_fisttp, fix_truncsi_i387_fisttp, fix_truncdi_i387_fisttp (define_insn "fix_trunc<mode>_i387_fisttp" [(set (match_operand:SWI248x 0 "memory_operand" "=m") (fix:SWI248x (match_operand 1 "register_operand" "f"))) @@ -4791,6 +4907,9 @@ [(set_attr "type" "fisttp") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fix_trunchi_i387_fisttp_with_temp, fix_truncsi_i387_fisttp_with_temp +;; fix_truncdi_i387_fisttp_with_temp (define_insn "fix_trunc<mode>_i387_fisttp_with_temp" [(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m,?r") (fix:SWI248x (match_operand 1 "register_operand" "f,f"))) @@ -4918,6 +5037,8 @@ (use (match_dup 3)) (clobber (match_dup 5))])]) +;; Expands to: +;; fix_trunchi_i387, fix_truncsi_i387 (define_insn "fix_trunc<mode>_i387" [(set (match_operand:SWI24 0 "memory_operand" "=m") (fix:SWI24 (match_operand 1 "register_operand" "f"))) @@ -4931,6 +5052,8 @@ (set_attr "i387_cw" "trunc") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fix_trunchi_i387_with_temp, fix_truncsi_i387_with_temp (define_insn "fix_trunc<mode>_i387_with_temp" [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r") (fix:SWI24 (match_operand 1 "register_operand" "f,f"))) @@ -4998,6 +5121,8 @@ ;; wants to be able to do this between registers. Thankfully, LRA ;; will fix this up for us during register allocation. +;; Expands to: +;; floathisf2, floathidf2, floathixf2 (define_insn "floathi<mode>2" [(set (match_operand:X87MODEF 0 "register_operand" "=f") (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m")))] @@ -5010,6 +5135,8 @@ (set_attr "znver1_decode" "double") (set_attr "fp_int_src" "true")]) +;; Expands to: +;; floatsixf2, floatdixf2 (define_insn "float<SWI48x:mode>xf2" [(set (match_operand:XF 0 "register_operand" "=f") (float:XF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))] @@ -5020,6 +5147,8 @@ (set_attr "znver1_decode" "double") (set_attr "fp_int_src" "true")]) +;; Expands to: +;; floatsisf2, floatdisf2, floatsidf2, floatdidf2 (define_expand "float<SWI48:mode><MODEF:mode>2" [(set (match_operand:MODEF 0 "register_operand") (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))] @@ -5045,6 +5174,8 @@ } }) +;; Expands to: +;; *floatsisf2_mixed, *floatdisf2_mixed, *floatsidf2_mixed, *floatdidf2_mixed (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed" [(set (match_operand:MODEF 0 "register_operand" "=f,v,v") (float:MODEF @@ -5081,6 +5212,8 @@ (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")] (symbol_ref "true")))]) +;; Expands to: +;; *floatsisf2_i387, *floatsidf2_i387, *floatdisf2_i387, *floatdidf2_i387 (define_insn "*float<SWI48x:mode><MODEF:mode>2_i387" [(set (match_operand:MODEF 0 "register_operand" "=f") (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))] @@ -5206,6 +5339,9 @@ ;; Avoid store forwarding (partial memory) stall penalty ;; by passing DImode value through XMM registers. */ +;; Expands to: +;; floatdisf2_i387_with_xmm, floatdidf2_i387_with_xmm +;; floatdixf2_i387_with_xmm (define_insn "floatdi<X87MODEF:mode>2_i387_with_xmm" [(set (match_operand:X87MODEF 0 "register_operand" "=f,f") (float:X87MODEF @@ -5259,6 +5395,8 @@ && reload_completed" [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]) +;; Expands to: +;; floatunsqisf2, floatunshisf2, floatunsqidf2, floatunshidf2 (define_expand "floatuns<SWI12:mode><MODEF:mode>2" [(set (match_operand:MODEF 0 "register_operand") (unsigned_float:MODEF @@ -5294,6 +5432,8 @@ [(set_attr "type" "multi") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; floatunssisf2, floatunssidf2, floatunssixf2 (define_expand "floatunssi<mode>2" [(parallel [(set (match_operand:X87MODEF 0 "register_operand") @@ -5384,6 +5524,8 @@ ;; Add instructions +;; Expands to: +;; addqi3, addhi3, addsi3, adddi3, addti3 (define_expand "add<mode>3" [(set (match_operand:SDWIM 0 "nonimmediate_operand") (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") @@ -5415,6 +5557,8 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);") +;; Expands to: +;; *addsi_1, *adddi_1 (define_insn "*add<mode>_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r") (plus:SWI48 @@ -5726,6 +5870,8 @@ [(set (match_dup 0) (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]) +;; Expands to: +;; *addqi_2, *addhi_2, *addsi_2, *adddi_2 (define_insn "*add<mode>_2" [(set (reg FLAGS_REG) (compare @@ -5815,6 +5961,8 @@ (const_string "*"))) (set_attr "mode" "SI")]) +;; Expands to: +;; *addqi_3, *addhi_3, *addsi_3, *adddi_3 (define_insn "*add<mode>_3" [(set (reg FLAGS_REG) (compare @@ -5952,6 +6100,8 @@ ; Also carry flag is reversed compared to cmp, so this conversion is valid ; only for comparisons not depending on it. +;; Expands to: +;; *addqi_4, *addhi_4, *addsi_4 (define_insn "*add<mode>_4" [(set (reg FLAGS_REG) (compare @@ -5989,6 +6139,8 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *addqi_5, *addhi_5, *addsi_5, *adddi_5 (define_insn "*add<mode>_5" [(set (reg FLAGS_REG) (compare @@ -6089,6 +6241,8 @@ (set_attr "mode" "QI")]) ;; Add with jump on overflow. +;; Expands to: +;; addvqi4, addvhi4, addvsi4, addvdi4 (define_expand "addv<mode>4" [(parallel [(set (reg:CCO FLAGS_REG) (eq:CCO (plus:<DWI> @@ -6114,6 +6268,8 @@ operands[4] = gen_rtx_SIGN_EXTEND (<DWI>mode, operands[2]); }) +;; Expands to: +;; *addvqi4, *addvhi4, *addvsi4, *addvdi4 (define_insn "*addv<mode>4" [(set (reg:CCO FLAGS_REG) (eq:CCO (plus:<DWI> @@ -6131,6 +6287,8 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *addvqi4_1, *addvhi4_1, *addvsi4_1, *addvdi4_1 (define_insn "*addv<mode>4_1" [(set (reg:CCO FLAGS_REG) (eq:CCO (plus:<DWI> @@ -6156,6 +6314,8 @@ (const_string "4")] (const_string "<MODE_SIZE>")))]) +;; Expands to: +;; uaddvqi4, uaddvhi4, uaddvsi4, uaddvdi4 (define_expand "uaddv<mode>4" [(parallel [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6316,6 +6476,8 @@ ;; Subtract instructions +;; Expands to: +;; subqi3, subhi3, subsi3, subdi3, subti3 (define_expand "sub<mode>3" [(set (match_operand:SDWIM 0 "nonimmediate_operand") (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") @@ -6345,6 +6507,8 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);") +;; Expands to: +;; *subqi_1, *subhi_1, *subsi_1, *subdi_1 (define_insn "*sub<mode>_1" [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>") (minus:SWI @@ -6378,6 +6542,8 @@ [(set_attr "type" "alu1") (set_attr "mode" "QI")]) +;; Expands to: +;; *subqi_2, *subhi_2, *subsi_2, *subdi_2 (define_insn "*sub<mode>_2" [(set (reg FLAGS_REG) (compare @@ -6410,6 +6576,8 @@ (set_attr "mode" "SI")]) ;; Subtract with jump on overflow. +;; Expands to: +;; subvqi4, subvhi4, subvsi4, subvdi4 (define_expand "subv<mode>4" [(parallel [(set (reg:CCO FLAGS_REG) (eq:CCO (minus:<DWI> @@ -6435,6 +6603,8 @@ operands[4] = gen_rtx_SIGN_EXTEND (<DWI>mode, operands[2]); }) +;; Expands to: +;; *subvqi4, *subvhi4, *subvsi4, *subvdi4 (define_insn "*subv<mode>4" [(set (reg:CCO FLAGS_REG) (eq:CCO (minus:<DWI> @@ -6452,6 +6622,8 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *subvqi4_1, *subvhi4_1, *subvsi4_1, *subvdi4_1 (define_insn "*subv<mode>4_1" [(set (reg:CCO FLAGS_REG) (eq:CCO (minus:<DWI> @@ -6477,6 +6649,8 @@ (const_string "4")] (const_string "<MODE_SIZE>")))]) +;; Expands to: +;; usubvqi4, usubvhi4, usubvsi4, usubvdi4 (define_expand "usubv<mode>4" [(parallel [(set (reg:CC FLAGS_REG) (compare:CC @@ -6491,6 +6665,8 @@ "" "ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);") +;; Expands to: +;; *subqi_3, *subhi_3, *subsi_3, *subdi_3 (define_insn "*sub<mode>_3" [(set (reg FLAGS_REG) (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0") @@ -6519,6 +6695,8 @@ ;; Add with carry and subtract with borrow +;; Expands to: +;; addqi3_carry, addhi3_carry, addsi3_carry, adddi3_carry (define_insn "add<mode>3_carry" [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>") (plus:SWI @@ -6553,6 +6731,8 @@ ;; There is no point to generate ADCX instruction. ADC is shorter and faster. +;; Expands to: +;; addcarrysi, addcarrydi (define_insn "addcarry<mode>" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6575,6 +6755,8 @@ (set_attr "pent_pair" "pu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; subqi3_carry, subhi3_carry, subsi3_carry, subdi3_carry (define_insn "sub<mode>3_carry" [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>") (minus:SWI @@ -6608,6 +6790,8 @@ (set_attr "pent_pair" "pu") (set_attr "mode" "SI")]) +;; Expands to: +;; subborrowsi, subborrowdi (define_insn "subborrow<mode>" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6641,6 +6825,9 @@ (clobber (match_scratch:QI 2))])] "!(MEM_P (operands[0]) && MEM_P (operands[1]))") +;; Expands to: +;; *addqi3_cconly_overflow_1, *addhi3_cconly_overflow_1 +;; *addsi3_cconly_overflow_1, *adddi3_cconly_overflow_1 (define_insn "*add<mode>3_cconly_overflow_1" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6654,6 +6841,9 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *addqi3_cconly_overflow_2, *addhi3_cconly_overflow_2 +;; *addsi3_cconly_overflow_2, *adddi3_cconly_overflow_2 (define_insn "*add<mode>3_cconly_overflow_2" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6667,6 +6857,9 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *addqi3_cc_overflow_1, *addhi3_cc_overflow_1, *addsi3_cc_overflow_1 +;; *adddi3_cc_overflow_1 (define_insn "*add<mode>3_cc_overflow_1" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6681,6 +6874,9 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *addqi3_cc_overflow_2, *addhi3_cc_overflow_2, *addsi3_cc_overflow_2 +;; *adddi3_cc_overflow_2 (define_insn "*add<mode>3_cc_overflow_2" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -6725,6 +6921,8 @@ ;; The patterns that match these are at the end of this file. +;; Expands to: +;; addxf3, subxf3 (define_expand "<plusminus_insn>xf3" [(set (match_operand:XF 0 "register_operand") (plusminus:XF @@ -6732,6 +6930,8 @@ (match_operand:XF 2 "register_operand")))] "TARGET_80387") +;; Expands to: +;; addsf3, subsf3, adddf3, subdf3 (define_expand "<plusminus_insn><mode>3" [(set (match_operand:MODEF 0 "register_operand") (plusminus:MODEF @@ -6742,6 +6942,8 @@ ;; Multiply instructions +;; Expands to: +;; mulhi3, mulsi3, muldi3 (define_expand "mul<mode>3" [(parallel [(set (match_operand:SWIM248 0 "register_operand") (mult:SWIM248 @@ -6777,6 +6979,8 @@ ;; ;; On BDVER1, all HI MULs use DoublePath +;; Expands to: +;; *mulhi3_1, *mulsi3_1, *muldi3_1 (define_insn "*mul<mode>3_1" [(set (match_operand:SWIM248 0 "register_operand" "=r,r,r") (mult:SWIM248 @@ -6867,6 +7071,8 @@ (set_attr "mode" "QI")]) ;; Multiply with jump on overflow. +;; Expands to: +;; mulvhi4, mulvsi4, mulvdi4 (define_expand "mulv<mode>4" [(parallel [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:<DWI> @@ -6891,6 +7097,8 @@ operands[4] = gen_rtx_SIGN_EXTEND (<DWI>mode, operands[2]); }) +;; Expands to: +;; *mulvsi4, *mulvdi4 (define_insn "*mulv<mode>4" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:<DWI> @@ -6945,6 +7153,8 @@ (set_attr "bdver1_decode" "double") (set_attr "mode" "HI")]) +;; Expands to: +;; *mulvhi4_1, *mulvsi4_1, *mulvdi4_1 (define_insn "*mulv<mode>4_1" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:<DWI> @@ -6991,6 +7201,8 @@ (const_string "4")] (const_string "<MODE_SIZE>")))]) +;; Expands to: +;; umulvhi4, umulvsi4, umulvdi4 (define_expand "umulv<mode>4" [(parallel [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:<DWI> @@ -7015,6 +7227,8 @@ operands[1] = force_reg (<MODE>mode, operands[1]); }) +;; Expands to: +;; *umulvhi4, *umulvsi4, *umulvdi4 (define_insn "*umulv<mode>4" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:<DWI> @@ -7039,6 +7253,8 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; mulvqi4, umulvqi4 (define_expand "mulvqi4" [(parallel [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:HI @@ -7060,6 +7276,8 @@ operands[1] = force_reg (QImode, operands[1]); }) +;; Expands to: +;; *mulvqi4, *umulvqi4 (define_insn "*mulvqi4" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:HI @@ -7084,6 +7302,8 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "QI")]) +;; Expands to: +;; mulsidi3, umulsidi3, mulditi3, umulditi3 (define_expand "mul<mode><dwi>3" [(parallel [(set (match_operand:<DWI> 0 "register_operand") (mult:<DWI> @@ -7093,6 +7313,8 @@ (match_operand:DWIH 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))])]) +;; Expands to: +;; mulqihi3, umulqihi3 (define_expand "mulqihi3" [(parallel [(set (match_operand:HI 0 "register_operand") (mult:HI @@ -7103,6 +7325,8 @@ (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") +;; Expands to: +;; *bmi2_umulsidi3_1, *bmi2_umulditi3_1 (define_insn "*bmi2_umul<mode><dwi>3_1" [(set (match_operand:DWIH 0 "register_operand" "=r") (mult:DWIH @@ -7121,6 +7345,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *umulsidi3_1, *umulditi3_1 (define_insn "*umul<mode><dwi>3_1" [(set (match_operand:<DWI> 0 "register_operand" "=r,A") (mult:<DWI> @@ -7172,6 +7398,8 @@ operands[5] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT); }) +;; Expands to: +;; *mulsidi3_1, *mulditi3_1 (define_insn "*mul<mode><dwi>3_1" [(set (match_operand:<DWI> 0 "register_operand" "=A") (mult:<DWI> @@ -7192,6 +7420,8 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *mulqihi3_1, *umulqihi3_1 (define_insn "*mulqihi3_1" [(set (match_operand:HI 0 "register_operand" "=a") (mult:HI @@ -7213,6 +7443,8 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "QI")]) +;; Expands to: +;; smulsi3_highpart, umulsi3_highpart, smuldi3_highpart, umuldi3_highpart (define_expand "<s>mul<mode>3_highpart" [(parallel [(set (match_operand:SWI48 0 "register_operand") (truncate:SWI48 @@ -7228,6 +7460,8 @@ "" "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));") +;; Expands to: +;; *smuldi3_highpart_1, *umuldi3_highpart_1 (define_insn "*<s>muldi3_highpart_1" [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI @@ -7253,6 +7487,8 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "DI")]) +;; Expands to: +;; *smulsi3_highpart_1, *umulsi3_highpart_1 (define_insn "*<s>mulsi3_highpart_1" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI @@ -7277,6 +7513,8 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "SI")]) +;; Expands to: +;; *smulsi3_highpart_zext, *umulsi3_highpart_zext (define_insn "*<s>mulsi3_highpart_zext" [(set (match_operand:DI 0 "register_operand" "=d") (zero_extend:DI (truncate:SI @@ -7309,6 +7547,8 @@ (match_operand:XF 2 "register_operand")))] "TARGET_80387") +;; Expands to: +;; mulsf3, muldf3 (define_expand "mul<mode>3" [(set (match_operand:MODEF 0 "register_operand") (mult:MODEF (match_operand:MODEF 1 "register_operand") @@ -7354,6 +7594,8 @@ ;; Divmod instructions. +;; Expands to: +;; divmodhi4, divmodsi4, divmoddi4 (define_expand "divmod<mode>4" [(parallel [(set (match_operand:SWIM248 0 "register_operand") (div:SWIM248 @@ -7452,6 +7694,8 @@ [(set_attr "type" "multi") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *divmodhi4_noext, *divmodsi4_noext, *divmoddi4_noext (define_insn "*divmod<mode>4_noext" [(set (match_operand:SWIM248 0 "register_operand" "=a") (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0") @@ -7527,6 +7771,8 @@ [(set_attr "type" "idiv") (set_attr "mode" "QI")]) +;; Expands to: +;; udivmodhi4, udivmodsi4, udivmoddi4 (define_expand "udivmod<mode>4" [(parallel [(set (match_operand:SWIM248 0 "register_operand") (udiv:SWIM248 @@ -7624,6 +7870,8 @@ [(set_attr "type" "multi") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *udivmodhi4_noext, *udivmodsi4_noext, *udivmoddi4_noext (define_insn "*udivmod<mode>4_noext" [(set (match_operand:SWIM248 0 "register_operand" "=a") (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0") @@ -7783,6 +8031,8 @@ (set_attr "mode" "QI,QI,QI,SI") (set_attr "pent_pair" "uv,np,uv,np")]) +;; Expands to: +;; *testqi_1, *testhi_1, *testsi_1 (define_insn "*test<mode>_1" [(set (reg FLAGS_REG) (compare @@ -7863,6 +8113,8 @@ (set_attr "mode" "QI")]) ;; Combine likes to form bit extractions for some tests. Humor it. +;; Expands to: +;; *testqi_ext_3, *testqi_ext_3 (define_insn "*testqi_ext_3" [(set (reg FLAGS_REG) (compare (zero_extract:SWI48 @@ -7999,6 +8251,9 @@ (define_mode_iterator SWI1248_AVX512BW [QI HI (SI "TARGET_AVX512BW") (DI "TARGET_AVX512BW")]) +;; Expands to: +;; *kandqi, *korqi, *kxorqi, *kandhi, *korhi, *kxorhi, *kandsi, *korsi +;; *kxorsi, *kanddi, *kordi, *kxordi (define_insn "*k<logic><mode>" [(set (match_operand:SWI1248_AVX512BW 0 "mask_reg_operand" "=k") (any_logic:SWI1248_AVX512BW (match_operand:SWI1248_AVX512BW 1 "mask_reg_operand" "k") @@ -8018,6 +8273,8 @@ ;; and sometimes to QImode registers. If this is considered useful, ;; it should be done with splitters. +;; Expands to: +;; andqi3, andhi3, andsi3, anddi3 (define_expand "and<mode>3" [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") (and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") @@ -8225,6 +8482,8 @@ [(set_attr "type" "alu1") (set_attr "mode" "QI")]) +;; Expands to: +;; kandnqi, kandnhi (define_insn "kandn<mode>" [(set (match_operand:SWI12 0 "register_operand" "=r,&r,!k") (and:SWI12 @@ -8418,6 +8677,8 @@ [(set_attr "type" "alu") (set_attr "mode" "QI,QI,SI")]) +;; Expands to: +;; *andqi_2, *andhi_2, *andsi_2 (define_insn "*and<mode>_2" [(set (reg FLAGS_REG) (compare (and:SWI124 @@ -8602,6 +8863,8 @@ ;; %%% This used to optimize known byte-wide and operations to memory. ;; If this is considered useful, it should be done with splitters. +;; Expands to: +;; iorqi3, xorqi3, iorhi3, xorhi3, iorsi3, xorsi3, iordi3, xordi3 (define_expand "<code><mode>3" [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") (any_or:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") @@ -8609,6 +8872,8 @@ "" "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") +;; Expands to: +;; *iorsi_1, *xorsi_1, *iordi_1, *xordi_1 (define_insn "*<code><mode>_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,k") (any_or:SWI48 @@ -8640,6 +8905,8 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") +;; Expands to: +;; *iorhi_1, *xorhi_1 (define_insn "*<code>hi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k") (any_or:HI @@ -8655,6 +8922,8 @@ (set_attr "mode" "HI")]) ;; %%% Potential partial reg stall on alternative 2. What to do? +;; Expands to: +;; *iorqi_1, *xorqi_1 (define_insn "*<code>qi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r,!k") (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,k") @@ -8670,6 +8939,8 @@ (set_attr "mode" "QI,QI,SI,HI")]) ;; See comment for addsi_1_zext why we do use nonimmediate_operand +;; Expands to: +;; *iorsi_1_zext, *xorsi_1_zext (define_insn "*<code>si_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI @@ -8681,6 +8952,8 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) +;; Expands to: +;; *iorsi_1_zext_imm, *xorsi_1_zext_imm (define_insn "*<code>si_1_zext_imm" [(set (match_operand:DI 0 "register_operand" "=r") (any_or:DI @@ -8692,6 +8965,8 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) +;; Expands to: +;; *iorqi_1_slp, *xorqi_1_slp (define_insn "*<code>qi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m")) (any_or:QI (match_dup 0) @@ -8703,6 +8978,9 @@ [(set_attr "type" "alu1") (set_attr "mode" "QI")]) +;; Expands to: +;; *iorqi_2, *xorqi_2, *iorhi_2, *xorhi_2, *iorsi_2, *xorsi_2, *iordi_2 +;; *xordi_2 (define_insn "*<code><mode>_2" [(set (reg FLAGS_REG) (compare (any_or:SWI @@ -8717,6 +8995,8 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; kxnorqi, kxnorhi (define_insn "kxnor<mode>" [(set (match_operand:SWI12 0 "register_operand" "=r,!k") (not:SWI12 @@ -8734,6 +9014,8 @@ (set_attr "prefix" "*,vex") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; kxnorsi, kxnordi (define_insn "kxnor<mode>" [(set (match_operand:SWI48x 0 "register_operand" "=r,!k") (not:SWI48x @@ -8829,6 +9111,8 @@ ;; See comment for addsi_1_zext why we do use nonimmediate_operand ;; ??? Special case for immediate operand is missing - it is tricky. +;; Expands to: +;; *iorsi_2_zext, *xorsi_2_zext (define_insn "*<code>si_2_zext" [(set (reg FLAGS_REG) (compare (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0") @@ -8842,6 +9126,8 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) +;; Expands to: +;; *iorsi_2_zext_imm, *xorsi_2_zext_imm (define_insn "*<code>si_2_zext_imm" [(set (reg FLAGS_REG) (compare (any_or:SI @@ -8856,6 +9142,8 @@ [(set_attr "type" "alu") (set_attr "mode" "SI")]) +;; Expands to: +;; *iorqi_2_slp, *xorqi_2_slp (define_insn "*<code>qi_2_slp" [(set (reg FLAGS_REG) (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") @@ -8870,6 +9158,9 @@ [(set_attr "type" "alu1") (set_attr "mode" "QI")]) +;; Expands to: +;; *iorqi_3, *xorqi_3, *iorhi_3, *xorhi_3, *iorsi_3, *xorsi_3, *iordi_3 +;; *xordi_3 (define_insn "*<code><mode>_3" [(set (reg FLAGS_REG) (compare (any_or:SWI @@ -8883,6 +9174,8 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *iorqi_ext_0, *xorqi_ext_0 (define_insn "*<code>qi_ext_0" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") (const_int 8) @@ -8901,6 +9194,8 @@ (set_attr "modrm" "1") (set_attr "mode" "QI")]) +;; Expands to: +;; *iorqi_ext_1, *xorqi_ext_1 (define_insn "*<code>qi_ext_1" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q") (const_int 8) @@ -8920,6 +9215,8 @@ (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) +;; Expands to: +;; *iorqi_ext_2, *xorqi_ext_2 (define_insn "*<code>qi_ext_2" [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q") (const_int 8) @@ -9029,6 +9326,8 @@ ;; Negation instructions +;; Expands to: +;; negqi2, neghi2, negsi2, negdi2, negti2 (define_expand "neg<mode>2" [(set (match_operand:SDWIM 0 "nonimmediate_operand") (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))] @@ -9058,6 +9357,8 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);") +;; Expands to: +;; *negqi2_1, *neghi2_1, *negsi2_1, *negdi2_1 (define_insn "*neg<mode>2_1" [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m") (neg:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))) @@ -9084,6 +9385,8 @@ ;; it really performs (compare 0 x), which leaves us with the zero ;; flag being the only useful item. +;; Expands to: +;; *negqi2_cmpz, *neghi2_cmpz, *negsi2_cmpz, *negdi2_cmpz (define_insn "*neg<mode>2_cmpz" [(set (reg:CCZ FLAGS_REG) (compare:CCZ @@ -9115,6 +9418,8 @@ (set_attr "mode" "SI")]) ;; Negate with jump on overflow. +;; Expands to: +;; negvqi3, negvhi3, negvsi3, negvdi3 (define_expand "negv<mode>3" [(parallel [(set (reg:CCO FLAGS_REG) (ne:CCO (match_operand:SWI 1 "register_operand") @@ -9132,6 +9437,8 @@ <MODE>mode); }) +;; Expands to: +;; *negvqi3, *negvhi3, *negvsi3, *negvdi3 (define_insn "*negv<mode>3" [(set (reg:CCO FLAGS_REG) (ne:CCO (match_operand:SWI 1 "nonimmediate_operand" "0") @@ -9146,12 +9453,16 @@ ;; Changing of sign for FP values is doable using integer unit too. +;; Expands to: +;; abssf2, negsf2, absdf2, negdf2, absxf2, negxf2 (define_expand "<code><mode>2" [(set (match_operand:X87MODEF 0 "register_operand") (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") +;; Expands to: +;; *absnegsf2_mixed, *absnegdf2_mixed (define_insn "*absneg<mode>2_mixed" [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r") (match_operator:MODEF 3 "absneg_operator" @@ -9166,6 +9477,8 @@ ] (symbol_ref "true")))]) +;; Expands to: +;; *absnegsf2_i387, *absnegdf2_i387, *absnegxf2_i387 (define_insn "*absneg<mode>2_i387" [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r") (match_operator:X87MODEF 3 "absneg_operator" @@ -9175,6 +9488,8 @@ "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "#") +;; Expands to: +;; abstf2, negtf2 (define_expand "<code>tf2" [(set (match_operand:TF 0 "register_operand") (absneg:TF (match_operand:TF 1 "register_operand")))] @@ -9315,6 +9630,8 @@ ;; Conditionalize these after reload. If they match before reload, we ;; lose the clobber and ability to use integer instructions. +;; Expands to: +;; *abssf2_1, *negsf2_1, *absdf2_1, *negdf2_1, *absxf2_1, *negxf2_1 (define_insn "*<code><mode>2_1" [(set (match_operand:X87MODEF 0 "register_operand" "=f") (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))] @@ -9325,6 +9642,8 @@ [(set_attr "type" "fsgn") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *absextendsfdf2, *negextendsfdf2 (define_insn "*<code>extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=f") (absneg:DF (float_extend:DF @@ -9334,6 +9653,8 @@ [(set_attr "type" "fsgn") (set_attr "mode" "DF")]) +;; Expands to: +;; *absextendsfxf2, *negextendsfxf2 (define_insn "*<code>extendsfxf2" [(set (match_operand:XF 0 "register_operand" "=f") (absneg:XF (float_extend:XF @@ -9343,6 +9664,8 @@ [(set_attr "type" "fsgn") (set_attr "mode" "XF")]) +;; Expands to: +;; *absextenddfxf2, *negextenddfxf2 (define_insn "*<code>extenddfxf2" [(set (match_operand:XF 0 "register_operand" "=f") (absneg:XF (float_extend:XF @@ -9357,6 +9680,8 @@ (define_mode_iterator CSGNMODE [SF DF TF]) (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")]) +;; Expands to: +;; copysignsf3, copysigndf3, copysigntf3 (define_expand "copysign<mode>3" [(match_operand:CSGNMODE 0 "register_operand") (match_operand:CSGNMODE 1 "nonmemory_operand") @@ -9379,6 +9704,8 @@ [(const_int 0)] "ix86_split_copysign_const (operands); DONE;") +;; Expands to: +;; copysignsf3_var, copysigndf3_var, copysigntf3_var (define_insn "copysign<mode>3_var" [(set (match_operand:CSGNMODE 0 "register_operand" "=x,x,x,x,x") (unspec:CSGNMODE @@ -9409,12 +9736,16 @@ ;; One complement instructions +;; Expands to: +;; one_cmplqi2, one_cmplhi2, one_cmplsi2, one_cmpldi2 (define_expand "one_cmpl<mode>2" [(set (match_operand:SWIM 0 "nonimmediate_operand") (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand")))] "" "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;") +;; Expands to: +;; *one_cmplsi2_1, *one_cmpldi2_1 (define_insn "*one_cmpl<mode>2_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,k") (not:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,k")))] @@ -9474,6 +9805,8 @@ [(set_attr "type" "negnot") (set_attr "mode" "SI")]) +;; Expands to: +;; *one_cmplqi2_2, *one_cmplhi2_2, *one_cmplsi2_2, *one_cmpldi2_2 (define_insn "*one_cmpl<mode>2_2" [(set (reg FLAGS_REG) (compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")) @@ -9551,6 +9884,9 @@ ;; shift pair, instead using moves and sign extension for counts greater ;; than 31. +;; Expands to: +;; *shiftlqi3, *shiftrqi3, *shiftlhi3, *shiftrhi3, *shiftlsi3, *shiftrsi3 +;; *shiftldi3, *shiftrdi3 (define_insn "*<mshift><mode>3" [(set (match_operand:SWI1248_AVX512BWDQ 0 "register_operand" "=k") (any_lshift:SWI1248_AVX512BWDQ (match_operand:SWI1248_AVX512BWDQ 1 "register_operand" "k") @@ -9560,6 +9896,8 @@ [(set_attr "type" "msklog") (set_attr "prefix" "vex")]) +;; Expands to: +;; ashlqi3, ashlhi3, ashlsi3, ashldi3, ashlti3 (define_expand "ashl<mode>3" [(set (match_operand:SDWIM 0 "<shift_operand>") (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>") @@ -9567,6 +9905,8 @@ "" "ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;") +;; Expands to: +;; *ashldi3_doubleword, *ashlti3_doubleword (define_insn "*ashl<mode>3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=&r,r") (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "n,0") @@ -9634,6 +9974,8 @@ (set_attr "amdfam10_decode" "vector") (set_attr "bdver1_decode" "vector")]) +;; Expands to: +;; x86_shiftsi_adj_1, x86_shiftdi_adj_1 (define_expand "x86_shift<mode>_adj_1" [(set (reg:CCZ FLAGS_REG) (compare:CCZ (and:QI (match_operand:QI 2 "register_operand") @@ -9650,6 +9992,8 @@ "TARGET_CMOVE" "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));") +;; Expands to: +;; x86_shiftsi_adj_2, x86_shiftdi_adj_2 (define_expand "x86_shift<mode>_adj_2" [(use (match_operand:SWI48 0 "register_operand")) (use (match_operand:SWI48 1 "register_operand")) @@ -9680,6 +10024,8 @@ }) ;; Avoid useless masking of count operand. +;; Expands to: +;; *ashlsi3_mask, *ashldi3_mask (define_insn "*ashl<mode>3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (ashift:SWI48 @@ -9698,6 +10044,8 @@ [(set_attr "type" "ishift") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi2_ashlsi3_1, *bmi2_ashldi3_1 (define_insn "*bmi2_ashl<mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") @@ -9707,6 +10055,8 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *ashlsi3_1, *ashldi3_1 (define_insn "*ashl<mode>3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,l,rm") @@ -10030,6 +10380,8 @@ ;; This pattern can't accept a variable shift count, since shifts by ;; zero don't affect the flags. We assume that shifts by constant ;; zero are optimized away. +;; Expands to: +;; *ashlqi3_cmp, *ashlhi3_cmp, *ashlsi3_cmp, *ashldi3_cmp (define_insn "*ashl<mode>3_cmp" [(set (reg FLAGS_REG) (compare @@ -10126,6 +10478,8 @@ (const_string "*"))) (set_attr "mode" "SI")]) +;; Expands to: +;; *ashlqi3_cconly, *ashlhi3_cconly, *ashlsi3_cconly, *ashldi3_cconly (define_insn "*ashl<mode>3_cconly" [(set (reg FLAGS_REG) (compare @@ -10174,6 +10528,9 @@ ;; See comment above `ashl<mode>3' about how this works. +;; Expands to: +;; lshrqi3, ashrqi3, lshrhi3, ashrhi3, lshrsi3, ashrsi3, lshrdi3, ashrdi3 +;; lshrti3, ashrti3 (define_expand "<shift_insn><mode>3" [(set (match_operand:SDWIM 0 "<shift_operand>") (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>") @@ -10182,6 +10539,8 @@ "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") ;; Avoid useless masking of count operand. +;; Expands to: +;; *lshrsi3_mask, *ashrsi3_mask, *lshrdi3_mask, *ashrdi3_mask (define_insn "*<shift_insn><mode>3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (any_shiftrt:SWI48 @@ -10313,6 +10672,8 @@ (set_attr "modrm" "0,1") (set_attr "mode" "SI")]) +;; Expands to: +;; x86_shiftsi_adj_3, x86_shiftdi_adj_3 (define_expand "x86_shift<mode>_adj_3" [(use (match_operand:SWI48 0 "register_operand")) (use (match_operand:SWI48 1 "register_operand")) @@ -10342,6 +10703,8 @@ DONE; }) +;; Expands to: +;; *bmi2_lshrsi3_1, *bmi2_ashrsi3_1, *bmi2_lshrdi3_1, *bmi2_ashrdi3_1 (define_insn "*bmi2_<shift_insn><mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") @@ -10351,6 +10714,8 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *lshrsi3_1, *ashrsi3_1, *lshrdi3_1, *ashrdi3_1 (define_insn "*<shift_insn><mode>3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (any_shiftrt:SWI48 @@ -10394,6 +10759,8 @@ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))] "operands[2] = gen_lowpart (<MODE>mode, operands[2]);") +;; Expands to: +;; *bmi2_lshrsi3_1_zext, *bmi2_ashrsi3_1_zext (define_insn "*bmi2_<shift_insn>si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI @@ -10404,6 +10771,8 @@ [(set_attr "type" "ishiftx") (set_attr "mode" "SI")]) +;; Expands to: +;; *lshrsi3_1_zext, *ashrsi3_1_zext (define_insn "*<shift_insn>si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI @@ -10448,6 +10817,8 @@ (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))] "operands[2] = gen_lowpart (SImode, operands[2]);") +;; Expands to: +;; *lshrqi3_1, *ashrqi3_1, *lshrhi3_1, *ashrhi3_1 (define_insn "*<shift_insn><mode>3_1" [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m") (any_shiftrt:SWI12 @@ -10472,6 +10843,8 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *lshrqi3_1_slp, *ashrqi3_1_slp (define_insn "*<shift_insn>qi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) (any_shiftrt:QI (match_dup 0) @@ -10501,6 +10874,9 @@ ;; This pattern can't accept a variable shift count, since shifts by ;; zero don't affect the flags. We assume that shifts by constant ;; zero are optimized away. +;; Expands to: +;; *lshrqi3_cmp, *ashrqi3_cmp, *lshrhi3_cmp, *ashrhi3_cmp, *lshrsi3_cmp +;; *ashrsi3_cmp, *lshrdi3_cmp, *ashrdi3_cmp (define_insn "*<shift_insn><mode>3_cmp" [(set (reg FLAGS_REG) (compare @@ -10533,6 +10909,8 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *lshrsi3_cmp_zext, *ashrsi3_cmp_zext (define_insn "*<shift_insn>si3_cmp_zext" [(set (reg FLAGS_REG) (compare @@ -10565,6 +10943,9 @@ (const_string "*"))) (set_attr "mode" "SI")]) +;; Expands to: +;; *lshrqi3_cconly, *ashrqi3_cconly, *lshrhi3_cconly, *ashrhi3_cconly +;; *lshrsi3_cconly, *ashrsi3_cconly, *lshrdi3_cconly, *ashrdi3_cconly (define_insn "*<shift_insn><mode>3_cconly" [(set (reg FLAGS_REG) (compare @@ -10597,6 +10978,8 @@ ;; Rotate instructions +;; Expands to: +;; rotlti3, rotrti3 (define_expand "<rotate_insn>ti3" [(set (match_operand:TI 0 "register_operand") (any_rotate:TI (match_operand:TI 1 "register_operand") @@ -10612,6 +10995,8 @@ DONE; }) +;; Expands to: +;; rotldi3, rotrdi3 (define_expand "<rotate_insn>di3" [(set (match_operand:DI 0 "shiftdi_operand") (any_rotate:DI (match_operand:DI 1 "shiftdi_operand") @@ -10629,6 +11014,8 @@ DONE; }) +;; Expands to: +;; rotlqi3, rotrqi3, rotlhi3, rotrhi3, rotlsi3, rotrsi3 (define_expand "<rotate_insn><mode>3" [(set (match_operand:SWIM124 0 "nonimmediate_operand") (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand") @@ -10637,6 +11024,8 @@ "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;") ;; Avoid useless masking of count operand. +;; Expands to: +;; *rotlsi3_mask, *rotrsi3_mask, *rotldi3_mask, *rotrdi3_mask (define_insn "*<rotate_insn><mode>3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (any_rotate:SWI48 @@ -10714,6 +11103,8 @@ split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]); }) +;; Expands to: +;; *bmi2_rorxsi3_1, *bmi2_rorxdi3_1 (define_insn "*bmi2_rorx<mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") @@ -10723,6 +11114,8 @@ [(set_attr "type" "rotatex") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *rotlsi3_1, *rotrsi3_1, *rotldi3_1, *rotrdi3_1 (define_insn "*<rotate_insn><mode>3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (any_rotate:SWI48 @@ -10789,6 +11182,8 @@ [(set_attr "type" "rotatex") (set_attr "mode" "SI")]) +;; Expands to: +;; *rotlsi3_1_zext, *rotrsi3_1_zext (define_insn "*<rotate_insn>si3_1_zext" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI @@ -10847,6 +11242,8 @@ [(set (match_dup 0) (zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))]) +;; Expands to: +;; *rotlqi3_1, *rotrqi3_1, *rotlhi3_1, *rotrhi3_1 (define_insn "*<rotate_insn><mode>3_1" [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m") (any_rotate:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "0") @@ -10870,6 +11267,8 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *rotlqi3_1_slp, *rotrqi3_1_slp (define_insn "*<rotate_insn>qi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) (any_rotate:QI (match_dup 0) @@ -11038,6 +11437,8 @@ DONE; }) +;; Expands to: +;; *btsi, *btdi (define_insn "*bt<mode>" [(set (reg:CCC FLAGS_REG) (compare:CCC @@ -11322,6 +11723,8 @@ ;; 0xffffffff is NaN, but not in normalized form, so we can't represent ;; it directly. +;; Expands to: +;; setcc_sf_sse, setcc_df_sse (define_insn "setcc_<mode>_sse" [(set (match_operand:MODEF 0 "register_operand" "=x,x") (match_operator:MODEF 3 "sse_comparison_operator" @@ -11433,6 +11836,8 @@ ;; Define combination compare-and-branch fp compare instructions to help ;; combine. +;; Expands to: +;; *jccsf_0_i387, *jccdf_0_i387, *jccxf_0_i387 (define_insn "*jcc<mode>_0_i387" [(set (pc) (if_then_else (match_operator:CCFP 0 "ix86_fp_comparison_operator" @@ -11446,6 +11851,8 @@ "TARGET_80387 && !TARGET_CMOVE" "#") +;; Expands to: +;; *jccsf_0_r_i387, *jccdf_0_r_i387, *jccxf_0_r_i387 (define_insn "*jcc<mode>_0_r_i387" [(set (pc) (if_then_else (match_operator:CCFP 0 "ix86_fp_comparison_operator" @@ -11485,6 +11892,8 @@ "TARGET_80387 && !TARGET_CMOVE" "#") +;; Expands to: +;; *jccsf_i387, *jccdf_i387 (define_insn "*jcc<mode>_i387" [(set (pc) (if_then_else (match_operator:CCFP 0 "ix86_fp_comparison_operator" @@ -11498,6 +11907,8 @@ "TARGET_80387 && !TARGET_CMOVE" "#") +;; Expands to: +;; *jccsf_r_i387, *jccdf_r_i387 (define_insn "*jcc<mode>_r_i387" [(set (pc) (if_then_else (match_operator:CCFP 0 "ix86_fp_comparison_operator" @@ -11511,6 +11922,8 @@ "TARGET_80387 && !TARGET_CMOVE" "#") +;; Expands to: +;; *jccusf_i387, *jccudf_i387, *jccuxf_i387 (define_insn "*jccu<mode>_i387" [(set (pc) (if_then_else (match_operator:CCFPU 0 "ix86_fp_comparison_operator" @@ -11524,6 +11937,8 @@ "TARGET_80387 && !TARGET_CMOVE" "#") +;; Expands to: +;; *jccusf_r_i387, *jccudf_r_i387, *jccuxf_r_i387 (define_insn "*jccu<mode>_r_i387" [(set (pc) (if_then_else (match_operator:CCFPU 0 "ix86_fp_comparison_operator" @@ -11579,6 +11994,9 @@ ;; with a precedence over other operators and is always put in the first ;; place. Swap condition and operands to match ficom instruction. +;; Expands to: +;; *jccsf_hi_i387, *jccdf_hi_i387, *jccxf_hi_i387, *jccsf_si_i387 +;; *jccdf_si_i387, *jccxf_si_i387 (define_insn "*jcc<X87MODEF:mode>_<SWI24:mode>_i387" [(set (pc) (if_then_else @@ -11596,6 +12014,9 @@ || optimize_function_for_size_p (cfun))" "#") +;; Expands to: +;; *jccsf_hi_r_i387, *jccdf_hi_r_i387, *jccxf_hi_r_i387, *jccsf_si_r_i387 +;; *jccdf_si_r_i387, *jccxf_si_r_i387 (define_insn "*jcc<X87MODEF:mode>_<SWI24:mode>_r_i387" [(set (pc) (if_then_else @@ -11662,6 +12083,8 @@ operands[0] = convert_memory_address (word_mode, operands[0]); }) +;; Expands to: +;; *indirect_jump, *indirect_jump (define_insn "*indirect_jump" [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw"))] "" @@ -11711,6 +12134,8 @@ operands[0] = convert_memory_address (word_mode, operands[0]); }) +;; Expands to: +;; *tablejump_1, *tablejump_1 (define_insn "*tablejump_1" [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rBw")) (use (label_ref (match_operand 1)))] @@ -11846,6 +12271,8 @@ DONE; }) +;; Expands to: +;; *call, *call (define_insn "*call" [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>BwBz")) (match_operand 1))] @@ -11862,6 +12289,8 @@ "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) +;; Expands to: +;; *sibcall, *sibcall (define_insn "*sibcall" [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UBsBz")) (match_operand 1))] @@ -11869,6 +12298,8 @@ "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) +;; Expands to: +;; *sibcall_memory, *sibcall_memory (define_insn "*sibcall_memory" [(call (mem:QI (match_operand:W 0 "memory_operand" "m")) (match_operand 1)) @@ -12020,6 +12451,8 @@ DONE; }) +;; Expands to: +;; *call_value, *call_value (define_insn "*call_value" [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>BwBz")) @@ -12039,6 +12472,8 @@ "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) +;; Expands to: +;; *sibcall_value, *sibcall_value (define_insn "*sibcall_value" [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UBsBz")) @@ -12047,6 +12482,8 @@ "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) +;; Expands to: +;; *sibcall_value_memory, *sibcall_value_memory (define_insn "*sibcall_value_memory" [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "memory_operand" "m")) @@ -12557,6 +12994,8 @@ ;; Bit manipulation instructions. +;; Expands to: +;; ffssi2, ffsdi2 (define_expand "ffs<mode>2" [(set (match_dup 2) (const_int -1)) (parallel [(set (match_dup 3) (match_dup 4)) @@ -12616,6 +13055,8 @@ ix86_expand_clear (operands[2]); }) +;; Expands to: +;; *tzcntsi_1, *tzcntdi_1 (define_insn "*tzcnt<mode>_1" [(set (reg:CCC FLAGS_REG) (compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm") @@ -12630,6 +13071,8 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bsfsi_1, *bsfdi_1 (define_insn "*bsf<mode>_1" [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_operand:SWI48 1 "nonimmediate_operand" "rm") @@ -12644,6 +13087,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; ctzhi2, ctzsi2, ctzdi2 (define_expand "ctz<mode>2" [(parallel [(set (match_operand:SWI248 0 "register_operand") @@ -12673,6 +13118,8 @@ ix86_expand_clear (operands[0]); }) +;; Expands to: +;; *ctzsi2_falsedep, *ctzdi2_falsedep (define_insn "*ctz<mode>2_falsedep" [(set (match_operand:SWI48 0 "register_operand" "=r") (ctz:SWI48 @@ -12695,6 +13142,8 @@ (set_attr "prefix_rep" "1") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *ctzhi2, *ctzsi2, *ctzdi2 (define_insn "*ctz<mode>2" [(set (match_operand:SWI248 0 "register_operand" "=r") (ctz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm"))) @@ -12722,6 +13171,8 @@ (const_string "0"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; clzhi2, clzsi2, clzdi2 (define_expand "clz<mode>2" [(parallel [(set (match_operand:SWI248 0 "register_operand") @@ -12742,6 +13193,8 @@ operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1); }) +;; Expands to: +;; clzhi2_lzcnt, clzsi2_lzcnt, clzdi2_lzcnt (define_expand "clz<mode>2_lzcnt" [(parallel [(set (match_operand:SWI248 0 "register_operand") @@ -12769,6 +13222,8 @@ ix86_expand_clear (operands[0]); }) +;; Expands to: +;; *clzsi2_lzcnt_falsedep, *clzdi2_lzcnt_falsedep (define_insn "*clz<mode>2_lzcnt_falsedep" [(set (match_operand:SWI48 0 "register_operand" "=r") (clz:SWI48 @@ -12782,6 +13237,8 @@ (set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *clzhi2_lzcnt, *clzsi2_lzcnt, *clzdi2_lzcnt (define_insn "*clz<mode>2_lzcnt" [(set (match_operand:SWI248 0 "register_operand" "=r") (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm"))) @@ -12793,6 +13250,8 @@ (set_attr "mode" "<MODE>")]) ;; BMI instructions. +;; Expands to: +;; *bmi_andn_si, *bmi_andn_di (define_insn "*bmi_andn_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (and:SWI48 @@ -12805,6 +13264,8 @@ (set_attr "btver2_decode" "direct, double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi_andn_si_ccno, *bmi_andn_di_ccno (define_insn "*bmi_andn_<mode>_ccno" [(set (reg FLAGS_REG) (compare @@ -12819,6 +13280,8 @@ (set_attr "btver2_decode" "direct, double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; bmi_bextr_si, bmi_bextr_di (define_insn "bmi_bextr_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "r,m") @@ -12831,6 +13294,8 @@ (set_attr "btver2_decode" "direct, double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi_bextr_si_ccz, *bmi_bextr_di_ccz (define_insn "*bmi_bextr_<mode>_ccz" [(set (reg:CCZ FLAGS_REG) (compare:CCZ @@ -12845,6 +13310,8 @@ (set_attr "btver2_decode" "direct, double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi_blsi_si, *bmi_blsi_di (define_insn "*bmi_blsi_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 @@ -12858,6 +13325,8 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi_blsmsk_si, *bmi_blsmsk_di (define_insn "*bmi_blsmsk_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (xor:SWI48 @@ -12872,6 +13341,8 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi_blsr_si, *bmi_blsr_di (define_insn "*bmi_blsr_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 @@ -12887,6 +13358,8 @@ (set_attr "mode" "<MODE>")]) ;; BMI2 instructions. +;; Expands to: +;; bmi2_bzhi_si3, bmi2_bzhi_di3 (define_expand "bmi2_bzhi_<mode>3" [(parallel [(set (match_operand:SWI48 0 "register_operand") @@ -12901,6 +13374,8 @@ "TARGET_BMI2" "operands[3] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);") +;; Expands to: +;; *bmi2_bzhi_si3, *bmi2_bzhi_di3 (define_insn "*bmi2_bzhi_<mode>3" [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 @@ -12919,6 +13394,8 @@ (define_mode_attr k [(SI "k") (DI "q")]) +;; Expands to: +;; *bmi2_bzhi_si3_1, *bmi2_bzhi_di3_1 (define_insn "*bmi2_bzhi_<mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 @@ -12934,6 +13411,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bmi2_bzhi_si3_1_ccz, *bmi2_bzhi_di3_1_ccz (define_insn "*bmi2_bzhi_<mode>3_1_ccz" [(set (reg:CCZ FLAGS_REG) (compare:CCZ @@ -12951,6 +13430,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; bmi2_pdep_si3, bmi2_pdep_di3 (define_insn "bmi2_pdep_<mode>3" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") @@ -12962,6 +13443,8 @@ (set_attr "prefix" "vex") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; bmi2_pext_si3, bmi2_pext_di3 (define_insn "bmi2_pext_<mode>3" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") @@ -12974,6 +13457,8 @@ (set_attr "mode" "<MODE>")]) ;; TBM instructions. +;; Expands to: +;; tbm_bextri_si, tbm_bextri_di (define_insn "tbm_bextri_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 @@ -12989,6 +13474,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blcfill_si, *tbm_blcfill_di (define_insn "*tbm_blcfill_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 @@ -13002,6 +13489,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blci_si, *tbm_blci_di (define_insn "*tbm_blci_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (ior:SWI48 @@ -13016,6 +13505,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blcic_si, *tbm_blcic_di (define_insn "*tbm_blcic_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 @@ -13030,6 +13521,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blcmsk_si, *tbm_blcmsk_di (define_insn "*tbm_blcmsk_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (xor:SWI48 @@ -13043,6 +13536,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blcs_si, *tbm_blcs_di (define_insn "*tbm_blcs_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (ior:SWI48 @@ -13056,6 +13551,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blsfill_si, *tbm_blsfill_di (define_insn "*tbm_blsfill_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (ior:SWI48 @@ -13069,6 +13566,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_blsic_si, *tbm_blsic_di (define_insn "*tbm_blsic_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (ior:SWI48 @@ -13083,6 +13582,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_t1mskc_si, *tbm_t1mskc_di (define_insn "*tbm_t1mskc_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (ior:SWI48 @@ -13097,6 +13598,8 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *tbm_tzmsk_si, *tbm_tzmsk_di (define_insn "*tbm_tzmsk_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 @@ -13147,6 +13650,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "HI")]) +;; Expands to: +;; popcounthi2, popcountsi2, popcountdi2 (define_expand "popcount<mode>2" [(parallel [(set (match_operand:SWI248 0 "register_operand") @@ -13174,6 +13679,8 @@ ix86_expand_clear (operands[0]); }) +;; Expands to: +;; *popcountsi2_falsedep, *popcountdi2_falsedep (define_insn "*popcount<mode>2_falsedep" [(set (match_operand:SWI48 0 "register_operand" "=r") (popcount:SWI48 @@ -13193,6 +13700,8 @@ (set_attr "type" "bitmanip") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *popcounthi2, *popcountsi2, *popcountdi2 (define_insn "*popcount<mode>2" [(set (match_operand:SWI248 0 "register_operand" "=r") (popcount:SWI248 @@ -13240,6 +13749,8 @@ } }) +;; Expands to: +;; *bswapsi2_movbe, *bswapdi2_movbe (define_insn "*bswap<mode>2_movbe" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,r,m") (bswap:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,m,r")))] @@ -13255,6 +13766,8 @@ (set_attr "prefix_extra" "*,1,1") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *bswapsi2, *bswapdi2 (define_insn "*bswap<mode>2" [(set (match_operand:SWI48 0 "register_operand" "=r") (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "0")))] @@ -13442,6 +13955,8 @@ "" "ix86_tls_descriptor_calls_expanded_in_cfun = true;") +;; Expands to: +;; *tls_global_dynamic_64_si, *tls_global_dynamic_64_di (define_insn "*tls_global_dynamic_64_<mode>" [(set (match_operand:P 0 "register_operand" "=a") (call:P @@ -13489,6 +14004,8 @@ [(set_attr "type" "multi") (set_attr "length" "22")]) +;; Expands to: +;; tls_global_dynamic_64_si, tls_global_dynamic_64_di (define_expand "tls_global_dynamic_64_<mode>" [(parallel [(set (match_operand:P 0 "register_operand") @@ -13541,6 +14058,8 @@ "" "ix86_tls_descriptor_calls_expanded_in_cfun = true;") +;; Expands to: +;; *tls_local_dynamic_base_64_si, *tls_local_dynamic_base_64_di (define_insn "*tls_local_dynamic_base_64_<mode>" [(set (match_operand:P 0 "register_operand" "=a") (call:P @@ -13579,6 +14098,8 @@ [(set_attr "type" "multi") (set_attr "length" "22")]) +;; Expands to: +;; tls_local_dynamic_base_64_si, tls_local_dynamic_base_64_di (define_expand "tls_local_dynamic_base_64_<mode>" [(parallel [(set (match_operand:P 0 "register_operand") @@ -13643,6 +14164,8 @@ (set_attr "memory" "load") (set_attr "imm_disp" "false")]) +;; Expands to: +;; *load_tp_si, *load_tp_di (define_insn "*load_tp_<mode>" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(const_int 0)] UNSPEC_TP))] @@ -13681,6 +14204,8 @@ (set_attr "memory" "load") (set_attr "imm_disp" "false")]) +;; Expands to: +;; *add_tp_si, *add_tp_di (define_insn "*add_tp_<mode>" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (unspec:P [(const_int 0)] UNSPEC_TP) @@ -13849,6 +14374,8 @@ ;; Gcc is slightly more smart about handling normal two address instructions ;; so use special patterns for add and mull. +;; Expands to: +;; *fop_sf_comm_mixed, *fop_df_comm_mixed (define_insn "*fop_<mode>_comm_mixed" [(set (match_operand:MODEF 0 "register_operand" "=f,x,v") (match_operator:MODEF 3 "binary_fp_operator" @@ -13875,6 +14402,8 @@ ] (const_string "*")))]) +;; Expands to: +;; *fop_sf_comm_i387, *fop_df_comm_i387 (define_insn "*fop_<mode>_comm_i387" [(set (match_operand:MODEF 0 "register_operand" "=f") (match_operator:MODEF 3 "binary_fp_operator" @@ -13902,6 +14431,8 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "SF")]) +;; Expands to: +;; *fop_sf_1_mixed, *fop_df_1_mixed (define_insn "*fop_<mode>_1_mixed" [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,v") (match_operator:MODEF 3 "binary_fp_operator" @@ -13938,6 +14469,8 @@ (const_string "*")))]) ;; This pattern is not fully shadowed by the pattern above. +;; Expands to: +;; *fop_sf_1_i387, *fop_df_1_i387 (define_insn "*fop_<mode>_1_i387" [(set (match_operand:MODEF 0 "register_operand" "=f,f") (match_operator:MODEF 3 "binary_fp_operator" @@ -13958,6 +14491,8 @@ (set_attr "mode" "<MODE>")]) ;; ??? Add SSE splitters for these! +;; Expands to: +;; *fop_sf_2_i387, *fop_sf_2_i387, *fop_df_2_i387, *fop_df_2_i387 (define_insn "*fop_<MODEF:mode>_2_i387" [(set (match_operand:MODEF 0 "register_operand" "=f") (match_operator:MODEF 3 "binary_fp_operator" @@ -13979,6 +14514,8 @@ (set_attr "fp_int_src" "true") (set_attr "mode" "<SWI24:MODE>")]) +;; Expands to: +;; *fop_sf_3_i387, *fop_sf_3_i387, *fop_df_3_i387, *fop_df_3_i387 (define_insn "*fop_<MODEF:mode>_3_i387" [(set (match_operand:MODEF 0 "register_operand" "=f") (match_operator:MODEF 3 "binary_fp_operator" @@ -14087,6 +14624,8 @@ (const_string "fop"))) (set_attr "mode" "XF")]) +;; Expands to: +;; *fop_xf_2_i387, *fop_xf_2_i387 (define_insn "*fop_xf_2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (match_operator:XF 3 "binary_fp_operator" @@ -14106,6 +14645,8 @@ (set_attr "fp_int_src" "true") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *fop_xf_3_i387, *fop_xf_3_i387 (define_insn "*fop_xf_3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (match_operator:XF 3 "binary_fp_operator" @@ -14125,6 +14666,8 @@ (set_attr "fp_int_src" "true") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *fop_xf_4_i387, *fop_xf_4_i387 (define_insn "*fop_xf_4_i387" [(set (match_operand:XF 0 "register_operand" "=f,f") (match_operator:XF 3 "binary_fp_operator" @@ -14142,6 +14685,8 @@ (const_string "fop"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *fop_xf_5_i387, *fop_xf_5_i387 (define_insn "*fop_xf_5_i387" [(set (match_operand:XF 0 "register_operand" "=f,f") (match_operator:XF 3 "binary_fp_operator" @@ -14159,6 +14704,8 @@ (const_string "fop"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; *fop_xf_6_i387, *fop_xf_6_i387 (define_insn "*fop_xf_6_i387" [(set (match_operand:XF 0 "register_operand" "=f,f") (match_operator:XF 3 "binary_fp_operator" @@ -14182,6 +14729,8 @@ ;; This pattern implements a no-op XFmode truncation for ;; all fancy i386 XFmode math functions. +;; Expands to: +;; truncxfsf2_i387_noop_unspec, truncxfdf2_i387_noop_unspec (define_insn "truncxf<mode>2_i387_noop_unspec" [(set (match_operand:MODEF 0 "register_operand" "=f") (unspec:MODEF [(match_operand:XF 1 "register_operand" "f")] @@ -14202,6 +14751,8 @@ (set_attr "amdfam10_decode" "direct") (set_attr "bdver1_decode" "direct")]) +;; Expands to: +;; sqrt_extendsfxf2_i387, sqrt_extenddfxf2_i387 (define_insn "sqrt_extend<mode>xf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF @@ -14237,6 +14788,8 @@ DONE; }) +;; Expands to: +;; *sqrtsf2_sse, *sqrtdf2_sse (define_insn "*sqrt<mode>2_sse" [(set (match_operand:MODEF 0 "register_operand" "=v") (sqrt:MODEF @@ -14252,6 +14805,8 @@ (set_attr "amdfam10_decode" "*") (set_attr "bdver1_decode" "*")]) +;; Expands to: +;; sqrtsf2, sqrtdf2 (define_expand "sqrt<mode>2" [(set (match_operand:MODEF 0 "register_operand") (sqrt:MODEF @@ -14323,6 +14878,8 @@ DONE; }) +;; Expands to: +;; fmodsf3, fmoddf3 (define_expand "fmod<mode>3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) @@ -14398,6 +14955,8 @@ DONE; }) +;; Expands to: +;; remaindersf3, remainderdf3 (define_expand "remainder<mode>3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) @@ -14440,6 +14999,8 @@ [(UNSPEC_SIN "sin") (UNSPEC_COS "cos")]) +;; Expands to: +;; *sinxf2_i387, *cosxf2_i387 (define_insn "*<sincos>xf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0")] @@ -14451,6 +15012,9 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; *sin_extendsfxf2_i387, *cos_extendsfxf2_i387, *sin_extenddfxf2_i387 +;; *cos_extenddfxf2_i387 (define_insn "*<sincos>_extend<mode>xf2_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(float_extend:XF @@ -14504,6 +15068,8 @@ && can_create_pseudo_p ()" [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]) +;; Expands to: +;; sincos_extendsfxf3_i387, sincos_extenddfxf3_i387 (define_insn "sincos_extend<mode>xf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(float_extend:XF @@ -14544,6 +15110,8 @@ [(set (match_dup 0) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]) +;; Expands to: +;; sincossf3, sincosdf3 (define_expand "sincos<mode>3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand")) @@ -14576,6 +15144,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; fptan_extendsfxf4_i387, fptan_extenddfxf4_i387 (define_insn "fptan_extend<mode>xf4_i387" [(set (match_operand:MODEF 0 "register_operand" "=f") (match_operand:MODEF 3 "const_double_operand" "F")) @@ -14606,6 +15176,8 @@ DONE; }) +;; Expands to: +;; tansf2, tandf2 (define_expand "tan<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -14638,6 +15210,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; fpatan_extendsfxf3_i387, fpatan_extenddfxf3_i387 (define_insn "fpatan_extend<mode>xf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(float_extend:XF @@ -14664,6 +15238,8 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations") +;; Expands to: +;; atan2sf3, atan2df3 (define_expand "atan2<mode>3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand")) @@ -14693,6 +15269,8 @@ emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ }) +;; Expands to: +;; atansf2, atandf2 (define_expand "atan<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -14735,6 +15313,8 @@ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ }) +;; Expands to: +;; asinsf2, asindf2 (define_expand "asin<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))] @@ -14779,6 +15359,8 @@ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */ }) +;; Expands to: +;; acossf2, acosdf2 (define_expand "acos<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))] @@ -14812,6 +15394,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; fyl2x_extendsfxf3_i387, fyl2x_extenddfxf3_i387 (define_insn "fyl2x_extend<mode>xf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(float_extend:XF @@ -14840,6 +15424,8 @@ emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */ }) +;; Expands to: +;; logsf2, logdf2 (define_expand "log<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -14870,6 +15456,8 @@ emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */ }) +;; Expands to: +;; log10sf2, log10df2 (define_expand "log10<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -14900,6 +15488,8 @@ emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ }) +;; Expands to: +;; log2sf2, log2df2 (define_expand "log2<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -14931,6 +15521,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; fyl2xp1_extendsfxf3_i387, fyl2xp1_extenddfxf3_i387 (define_insn "fyl2xp1_extend<mode>xf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(float_extend:XF @@ -14960,6 +15552,8 @@ DONE; }) +;; Expands to: +;; log1psf2, log1pdf2 (define_expand "log1p<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -14995,6 +15589,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; fxtract_extendsfxf3_i387, fxtract_extenddfxf3_i387 (define_insn "fxtract_extend<mode>xf3_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(float_extend:XF @@ -15021,6 +15617,8 @@ && flag_unsafe_math_optimizations" "operands[2] = gen_reg_rtx (XFmode);") +;; Expands to: +;; logbsf2, logbdf2 (define_expand "logb<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -15056,6 +15654,8 @@ DONE; }) +;; Expands to: +;; ilogbsf2, ilogbdf2 (define_expand "ilogb<mode>2" [(use (match_operand:SI 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -15148,6 +15748,8 @@ DONE; }) +;; Expands to: +;; expsf2, expdf2 (define_expand "exp<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))] @@ -15188,6 +15790,8 @@ DONE; }) +;; Expands to: +;; exp10sf2, exp10df2 (define_expand "exp10<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))] @@ -15228,6 +15832,8 @@ DONE; }) +;; Expands to: +;; exp2sf2, exp2df2 (define_expand "exp2<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))] @@ -15290,6 +15896,8 @@ emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */ }) +;; Expands to: +;; expm1sf2, expm1df2 (define_expand "expm1<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand"))] @@ -15332,6 +15940,8 @@ DONE; }) +;; Expands to: +;; ldexpsf3, ldexpdf3 (define_expand "ldexp<mode>3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) @@ -15372,6 +15982,8 @@ operands[3] = gen_reg_rtx (XFmode); }) +;; Expands to: +;; scalbsf3, scalbdf3 (define_expand "scalb<mode>3" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "general_operand")) @@ -15407,6 +16019,8 @@ && flag_unsafe_math_optimizations" "operands[2] = gen_reg_rtx (XFmode);") +;; Expands to: +;; significandsf2, significanddf2 (define_expand "significand<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -15424,6 +16038,8 @@ }) +;; Expands to: +;; sse4_1_roundsf2, sse4_1_rounddf2 (define_insn "sse4_1_round<mode>2" [(set (match_operand:MODEF 0 "register_operand" "=x") (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "x") @@ -15447,6 +16063,8 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) +;; Expands to: +;; rintsf2, rintdf2 (define_expand "rint<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -15481,6 +16099,8 @@ DONE; }) +;; Expands to: +;; roundsf2, rounddf2, roundxf2 (define_expand "round<mode>2" [(match_operand:X87MODEF 0 "register_operand") (match_operand:X87MODEF 1 "nonimmediate_operand")] @@ -15598,6 +16218,8 @@ [(set_attr "type" "fpspc") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fisthi2, fistsi2 (define_insn "fist<mode>2" [(set (match_operand:SWI24 0 "memory_operand" "=m") (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")] @@ -15607,6 +16229,8 @@ [(set_attr "type" "fpspc") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fisthi2_with_temp, fistsi2_with_temp (define_insn "fist<mode>2_with_temp" [(set (match_operand:SWI24 0 "register_operand" "=r") (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")] @@ -15634,18 +16258,25 @@ "reload_completed" [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))]) +;; Expands to: +;; lrintxfhi2, lrintxfsi2, lrintxfdi2 (define_expand "lrintxf<mode>2" [(set (match_operand:SWI248x 0 "nonimmediate_operand") (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387") +;; Expands to: +;; lrintsfsi2, lrintsfdi2, lrintdfsi2, lrintdfdi2 (define_expand "lrint<MODEF:mode><SWI48:mode>2" [(set (match_operand:SWI48 0 "nonimmediate_operand") (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")] UNSPEC_FIX_NOTRUNC))] "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH") +;; Expands to: +;; lroundsfhi2, lrounddfhi2, lroundxfhi2, lroundsfsi2, lrounddfsi2 +;; lroundxfsi2, lroundsfdi2, lrounddfdi2, lroundxfdi2 (define_expand "lround<X87MODEF:mode><SWI248x:mode>2" [(match_operand:SWI248x 0 "nonimmediate_operand") (match_operand:X87MODEF 1 "register_operand")] @@ -15728,6 +16359,8 @@ (set_attr "i387_cw" "<rounding>") (set_attr "mode" "XF")]) +;; Expands to: +;; frndintxf2_floor_i387, frndintxf2_ceil_i387, frndintxf2_trunc_i387 (define_insn "frndintxf2_<rounding>_i387" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0")] @@ -15741,6 +16374,8 @@ (set_attr "i387_cw" "<rounding>") (set_attr "mode" "XF")]) +;; Expands to: +;; floorxf2, ceilxf2, btruncxf2 (define_expand "<rounding_insn>xf2" [(parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_operand:XF 1 "register_operand")] @@ -15750,6 +16385,8 @@ && flag_unsafe_math_optimizations && !optimize_insn_for_size_p ()") +;; Expands to: +;; floorsf2, ceilsf2, btruncsf2, floordf2, ceildf2, btruncdf2 (define_expand "<rounding_insn><mode>2" [(parallel [(set (match_operand:MODEF 0 "register_operand") (unspec:MODEF [(match_operand:MODEF 1 "register_operand")] @@ -15857,6 +16494,8 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations") +;; Expands to: +;; nearbyintsf2, nearbyintdf2 (define_expand "nearbyint<mode>2" [(use (match_operand:MODEF 0 "register_operand")) (use (match_operand:MODEF 1 "register_operand"))] @@ -15908,6 +16547,8 @@ (set_attr "i387_cw" "<rounding>") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fistdi2_floor, fistdi2_ceil (define_insn "fistdi2_<rounding>" [(set (match_operand:DI 0 "memory_operand" "=m") (unspec:DI [(match_operand:XF 1 "register_operand" "f")] @@ -15922,6 +16563,8 @@ (set_attr "i387_cw" "<rounding>") (set_attr "mode" "DI")]) +;; Expands to: +;; fistdi2_floor_with_temp, fistdi2_ceil_with_temp (define_insn "fistdi2_<rounding>_with_temp" [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")] @@ -15968,6 +16611,8 @@ (use (match_dup 3)) (clobber (match_dup 5))])]) +;; Expands to: +;; fisthi2_floor, fisthi2_ceil, fistsi2_floor, fistsi2_ceil (define_insn "fist<mode>2_<rounding>" [(set (match_operand:SWI24 0 "memory_operand" "=m") (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")] @@ -15981,6 +16626,9 @@ (set_attr "i387_cw" "<rounding>") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; fisthi2_floor_with_temp, fisthi2_ceil_with_temp, fistsi2_floor_with_temp +;; fistsi2_ceil_with_temp (define_insn "fist<mode>2_<rounding>_with_temp" [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r") (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")] @@ -16022,6 +16670,8 @@ (use (match_dup 2)) (use (match_dup 3))])]) +;; Expands to: +;; lfloorxfhi2, lceilxfhi2, lfloorxfsi2, lceilxfsi2, lfloorxfdi2, lceilxfdi2 (define_expand "l<rounding_insn>xf<mode>2" [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand") (unspec:SWI248x [(match_operand:XF 1 "register_operand")] @@ -16031,6 +16681,9 @@ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations") +;; Expands to: +;; lfloorsfsi2, lceilsfsi2, lfloorsfdi2, lceilsfdi2, lfloordfsi2, lceildfsi2 +;; lfloordfdi2, lceildfdi2 (define_expand "l<rounding_insn><MODEF:mode><SWI48:mode>2" [(parallel [(set (match_operand:SWI48 0 "nonimmediate_operand") (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")] @@ -16052,6 +16705,8 @@ DONE; }) +;; Expands to: +;; fxamsf2_i387, fxamdf2_i387, fxamxf2_i387 (define_insn "fxam<mode>2_i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -16111,6 +16766,8 @@ DONE; }) +;; Expands to: +;; isinfsf2, isinfdf2 (define_expand "isinf<mode>2" [(use (match_operand:SI 0 "register_operand")) (use (match_operand:MODEF 1 "nonimmediate_operand"))] @@ -16219,6 +16876,8 @@ (set_attr "length_immediate" "0") (set_attr "modrm" "0")]) +;; Expands to: +;; movmemsi, movmemdi (define_expand "movmem<mode>" [(use (match_operand:BLK 0 "memory_operand")) (use (match_operand:BLK 1 "memory_operand")) @@ -16287,6 +16946,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *strmovdi_rex_1, *strmovdi_rex_1 (define_insn "*strmovdi_rex_1" [(set (mem:DI (match_operand:P 2 "register_operand" "0")) (mem:DI (match_operand:P 3 "register_operand" "1"))) @@ -16304,6 +16965,8 @@ (set_attr "memory" "both") (set_attr "mode" "DI")]) +;; Expands to: +;; *strmovsi_1, *strmovsi_1 (define_insn "*strmovsi_1" [(set (mem:SI (match_operand:P 2 "register_operand" "0")) (mem:SI (match_operand:P 3 "register_operand" "1"))) @@ -16320,6 +16983,8 @@ (set_attr "memory" "both") (set_attr "mode" "SI")]) +;; Expands to: +;; *strmovhi_1, *strmovhi_1 (define_insn "*strmovhi_1" [(set (mem:HI (match_operand:P 2 "register_operand" "0")) (mem:HI (match_operand:P 3 "register_operand" "1"))) @@ -16336,6 +17001,8 @@ (set_attr "memory" "both") (set_attr "mode" "HI")]) +;; Expands to: +;; *strmovqi_1, *strmovqi_1 (define_insn "*strmovqi_1" [(set (mem:QI (match_operand:P 2 "register_operand" "0")) (mem:QI (match_operand:P 3 "register_operand" "1"))) @@ -16369,6 +17036,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *rep_movdi_rex64, *rep_movdi_rex64 (define_insn "*rep_movdi_rex64" [(set (match_operand:P 2 "register_operand" "=c") (const_int 0)) (set (match_operand:P 0 "register_operand" "=D") @@ -16390,6 +17059,8 @@ (set_attr "memory" "both") (set_attr "mode" "DI")]) +;; Expands to: +;; *rep_movsi, *rep_movsi (define_insn "*rep_movsi" [(set (match_operand:P 2 "register_operand" "=c") (const_int 0)) (set (match_operand:P 0 "register_operand" "=D") @@ -16410,6 +17081,8 @@ (set_attr "memory" "both") (set_attr "mode" "SI")]) +;; Expands to: +;; *rep_movqi, *rep_movqi (define_insn "*rep_movqi" [(set (match_operand:P 2 "register_operand" "=c") (const_int 0)) (set (match_operand:P 0 "register_operand" "=D") @@ -16428,6 +17101,8 @@ (set_attr "memory" "both") (set_attr "mode" "QI")]) +;; Expands to: +;; setmemsi, setmemdi (define_expand "setmem<mode>" [(use (match_operand:BLK 0 "memory_operand")) (use (match_operand:SWI48 1 "nonmemory_operand")) @@ -16492,6 +17167,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *strsetdi_rex_1, *strsetdi_rex_1 (define_insn "*strsetdi_rex_1" [(set (mem:DI (match_operand:P 1 "register_operand" "0")) (match_operand:DI 2 "register_operand" "a")) @@ -16507,6 +17184,8 @@ (set_attr "memory" "store") (set_attr "mode" "DI")]) +;; Expands to: +;; *strsetsi_1, *strsetsi_1 (define_insn "*strsetsi_1" [(set (mem:SI (match_operand:P 1 "register_operand" "0")) (match_operand:SI 2 "register_operand" "a")) @@ -16521,6 +17200,8 @@ (set_attr "memory" "store") (set_attr "mode" "SI")]) +;; Expands to: +;; *strsethi_1, *strsethi_1 (define_insn "*strsethi_1" [(set (mem:HI (match_operand:P 1 "register_operand" "0")) (match_operand:HI 2 "register_operand" "a")) @@ -16535,6 +17216,8 @@ (set_attr "memory" "store") (set_attr "mode" "HI")]) +;; Expands to: +;; *strsetqi_1, *strsetqi_1 (define_insn "*strsetqi_1" [(set (mem:QI (match_operand:P 1 "register_operand" "0")) (match_operand:QI 2 "register_operand" "a")) @@ -16564,6 +17247,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *rep_stosdi_rex64, *rep_stosdi_rex64 (define_insn "*rep_stosdi_rex64" [(set (match_operand:P 1 "register_operand" "=c") (const_int 0)) (set (match_operand:P 0 "register_operand" "=D") @@ -16583,6 +17268,8 @@ (set_attr "memory" "store") (set_attr "mode" "DI")]) +;; Expands to: +;; *rep_stossi, *rep_stossi (define_insn "*rep_stossi" [(set (match_operand:P 1 "register_operand" "=c") (const_int 0)) (set (match_operand:P 0 "register_operand" "=D") @@ -16601,6 +17288,8 @@ (set_attr "memory" "store") (set_attr "mode" "SI")]) +;; Expands to: +;; *rep_stosqi, *rep_stosqi (define_insn "*rep_stosqi" [(set (match_operand:P 1 "register_operand" "=c") (const_int 0)) (set (match_operand:P 0 "register_operand" "=D") @@ -16723,6 +17412,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *cmpstrnqi_nz_1, *cmpstrnqi_nz_1 (define_insn "*cmpstrnqi_nz_1" [(set (reg:CC FLAGS_REG) (compare:CC (mem:BLK (match_operand:P 4 "register_operand" "0")) @@ -16761,6 +17452,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *cmpstrnqi_1, *cmpstrnqi_1 (define_insn "*cmpstrnqi_1" [(set (reg:CC FLAGS_REG) (if_then_else:CC (ne (match_operand:P 6 "register_operand" "2") @@ -16785,6 +17478,8 @@ (const_string "*"))) (set_attr "prefix_rep" "1")]) +;; Expands to: +;; strlensi, strlendi (define_expand "strlen<mode>" [(set (match_operand:P 0 "register_operand") (unspec:P [(match_operand:BLK 1 "general_operand") @@ -16807,6 +17502,8 @@ "" "ix86_current_function_needs_cld = 1;") +;; Expands to: +;; *strlenqi_1, *strlenqi_1 (define_insn "*strlenqi_1" [(set (match_operand:P 0 "register_operand" "=&c") (unspec:P [(mem:BLK (match_operand:P 5 "register_operand" "1")) @@ -16906,6 +17603,8 @@ ;; Conditional move instructions. +;; Expands to: +;; movqicc, movhicc, movsicc, movdicc (define_expand "mov<mode>cc" [(set (match_operand:SWIM 0 "register_operand") (if_then_else:SWIM (match_operand 1 "comparison_operator") @@ -16918,6 +17617,8 @@ ;; the register first winds up with `sbbl $0,reg', which is also weird. ;; So just document what we're doing explicitly. +;; Expands to: +;; x86_movsicc_0_m1, x86_movdicc_0_m1 (define_expand "x86_mov<mode>cc_0_m1" [(parallel [(set (match_operand:SWI48 0 "register_operand") @@ -16929,6 +17630,8 @@ (const_int 0))) (clobber (reg:CC FLAGS_REG))])]) +;; Expands to: +;; *x86_movsicc_0_m1, *x86_movdicc_0_m1 (define_insn "*x86_mov<mode>cc_0_m1" [(set (match_operand:SWI48 0 "register_operand" "=r") (if_then_else:SWI48 (match_operator 1 "ix86_carry_flag_operator" @@ -16949,6 +17652,8 @@ (set_attr "mode" "<MODE>") (set_attr "length_immediate" "0")]) +;; Expands to: +;; *x86_movsicc_0_m1_se, *x86_movdicc_0_m1_se (define_insn "*x86_mov<mode>cc_0_m1_se" [(set (match_operand:SWI48 0 "register_operand" "=r") (sign_extract:SWI48 (match_operator 1 "ix86_carry_flag_operator" @@ -16967,6 +17672,8 @@ (set_attr "mode" "<MODE>") (set_attr "length_immediate" "0")]) +;; Expands to: +;; *x86_movsicc_0_m1_neg, *x86_movdicc_0_m1_neg (define_insn "*x86_mov<mode>cc_0_m1_neg" [(set (match_operand:SWI48 0 "register_operand" "=r") (neg:SWI48 (match_operator 1 "ix86_carry_flag_operator" @@ -16983,6 +17690,8 @@ (set_attr "mode" "<MODE>") (set_attr "length_immediate" "0")]) +;; Expands to: +;; *movhicc_noc, *movsicc_noc, *movdicc_noc (define_insn "*mov<mode>cc_noc" [(set (match_operand:SWI248 0 "register_operand" "=r,r") (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" @@ -17123,6 +17832,8 @@ gcc_unreachable (); }) +;; Expands to: +;; movsfcc, movdfcc, movxfcc (define_expand "mov<mode>cc" [(set (match_operand:X87MODEF 0 "register_operand") (if_then_else:X87MODEF @@ -17256,6 +17967,8 @@ ;; the scalar versions to have only XMM registers as operands. ;; XOP conditional move +;; Expands to: +;; *xop_pcmov_sf, *xop_pcmov_df (define_insn "*xop_pcmov_<mode>" [(set (match_operand:MODEF 0 "register_operand" "=x") (if_then_else:MODEF @@ -17271,6 +17984,8 @@ ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator ;; are undefined in this condition, we're certain this is correct. +;; Expands to: +;; smaxsf3, sminsf3, smaxdf3, smindf3 (define_insn "<code><mode>3" [(set (match_operand:MODEF 0 "register_operand" "=x,v") (smaxmin:MODEF @@ -17299,6 +18014,8 @@ [(UNSPEC_IEEE_MAX "max") (UNSPEC_IEEE_MIN "min")]) +;; Expands to: +;; *ieee_smaxsf3, *ieee_sminsf3, *ieee_smaxdf3, *ieee_smindf3 (define_insn "*ieee_s<ieee_maxmin><mode>3" [(set (match_operand:MODEF 0 "register_operand" "=x,v") (unspec:MODEF @@ -17347,6 +18064,8 @@ }) ;; Conditional addition patterns +;; Expands to: +;; addqicc, addhicc, addsicc, adddicc (define_expand "add<mode>cc" [(match_operand:SWI 0 "register_operand") (match_operand 1 "ordered_comparison_operator") @@ -17367,6 +18086,8 @@ ;; ;; in proper program order. +;; Expands to: +;; pro_epilogue_adjust_stack_si_add, pro_epilogue_adjust_stack_di_add (define_insn "pro_epilogue_adjust_stack_<mode>_add" [(set (match_operand:P 0 "register_operand" "=r,r") (plus:P (match_operand:P 1 "register_operand" "0,r") @@ -17410,6 +18131,8 @@ (const_string "*"))) (set_attr "mode" "<MODE>")]) +;; Expands to: +;; pro_epilogue_adjust_stack_si_sub, pro_epilogue_adjust_stack_di_sub (define_insn "pro_epilogue_adjust_stack_<mode>_sub" [(set (match_operand:P 0 "register_operand" "=r") (minus:P (match_operand:P 1 "register_operand" "0") @@ -17421,6 +18144,8 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +;; Expands to: +;; allocate_stack_worker_probe_si, allocate_stack_worker_probe_di (define_insn "allocate_stack_worker_probe_<mode>" [(set (match_operand:P 0 "register_operand" "=a") (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")] @@ -17482,6 +18207,8 @@ DONE; }) +;; Expands to: +;; adjust_stack_and_probesi, adjust_stack_and_probedi (define_insn "adjust_stack_and_probe<mode>" [(set (match_operand:P 0 "register_operand" "=r") (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")] @@ -17494,6 +18221,8 @@ "* return output_adjust_stack_and_probe (operands[0]);" [(set_attr "type" "multi")]) +;; Expands to: +;; probe_stack_rangesi, probe_stack_rangedi (define_insn "probe_stack_range<mode>" [(set (match_operand:P 0 "register_operand" "=r") (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") @@ -18523,6 +19252,8 @@ DONE; }) +;; Expands to: +;; stack_protect_set_si, stack_protect_set_di (define_insn "stack_protect_set_<mode>" [(set (match_operand:PTR 0 "memory_operand" "=m") (unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")] @@ -18533,6 +19264,8 @@ "mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2" [(set_attr "type" "multi")]) +;; Expands to: +;; stack_tls_protect_set_si, stack_tls_protect_set_di (define_insn "stack_tls_protect_set_<mode>" [(set (match_operand:PTR 0 "memory_operand" "=m") (unspec:PTR [(match_operand:PTR 1 "const_int_operand" "i")] @@ -18571,6 +19304,8 @@ DONE; }) +;; Expands to: +;; stack_protect_test_si, stack_protect_test_di (define_insn "stack_protect_test_<mode>" [(set (match_operand:CCZ 0 "flags_reg_operand") (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") @@ -18581,6 +19316,8 @@ "mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}" [(set_attr "type" "multi")]) +;; Expands to: +;; stack_tls_protect_test_si, stack_tls_protect_test_di (define_insn "stack_tls_protect_test_<mode>" [(set (match_operand:CCZ 0 "flags_reg_operand") (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") @@ -18591,6 +19328,8 @@ "mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%@:%P2, %3|%3, <iptrsize> PTR %@:%P2}" [(set_attr "type" "multi")]) +;; Expands to: +;; sse4_2_crc32qi, sse4_2_crc32hi, sse4_2_crc32si (define_insn "sse4_2_crc32<mode>" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI @@ -18767,6 +19506,8 @@ (UNSPECV_XRSTORS "xrstors") (UNSPECV_XRSTORS64 "xrstors")]) +;; Expands to: +;; xsave, xsaveopt, xsavec, xsaves (define_insn "<xsave>" [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec_volatile:BLK @@ -18779,6 +19520,8 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) +;; Expands to: +;; xsave_rex64, xsaveopt_rex64, xsavec_rex64, xsaves_rex64 (define_insn "<xsave>_rex64" [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec_volatile:BLK @@ -18792,6 +19535,8 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) +;; Expands to: +;; xsave64, xsaveopt64, xsavec64, xsaves64 (define_insn "<xsave>" [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec_volatile:BLK @@ -18805,6 +19550,8 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 4"))]) +;; Expands to: +;; xrstor, xrstors (define_insn "<xrstor>" [(unspec_volatile:BLK [(match_operand:BLK 0 "memory_operand" "m") @@ -18817,6 +19564,8 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) +;; Expands to: +;; xrstor_rex64, xrstors_rex64 (define_insn "<xrstor>_rex64" [(unspec_volatile:BLK [(match_operand:BLK 0 "memory_operand" "m") @@ -18830,6 +19579,8 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 3"))]) +;; Expands to: +;; xrstor64, xrstors64 (define_insn "<xrstor>64" [(unspec_volatile:BLK [(match_operand:BLK 0 "memory_operand" "m") @@ -18919,6 +19670,8 @@ UNSPECV_LLWP_INTRINSIC)] "TARGET_LWP") +;; Expands to: +;; *lwp_llwpcbsi1, *lwp_llwpcbdi1 (define_insn "*lwp_llwpcb<mode>1" [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] UNSPECV_LLWP_INTRINSIC)] @@ -18943,6 +19696,8 @@ DONE; }) +;; Expands to: +;; lwp_slwpcbsi, lwp_slwpcbdi (define_insn "lwp_slwpcb<mode>" [(set (match_operand:P 0 "register_operand" "=r") (unspec_volatile:P [(const_int 0)] UNSPECV_SLWP_INTRINSIC))] @@ -18952,6 +19707,8 @@ (set_attr "mode" "<MODE>") (set_attr "length" "5")]) +;; Expands to: +;; lwp_lwpvalsi3, lwp_lwpvaldi3 (define_expand "lwp_lwpval<mode>3" [(unspec_volatile [(match_operand:SWI48 1 "register_operand" "r") (match_operand:SI 2 "nonimmediate_operand" "rm") @@ -18961,6 +19718,8 @@ ;; Avoid unused variable warning. "(void) operands[0];") +;; Expands to: +;; *lwp_lwpvalsi3_1, *lwp_lwpvaldi3_1 (define_insn "*lwp_lwpval<mode>3_1" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r") (match_operand:SI 1 "nonimmediate_operand" "rm") @@ -18973,6 +19732,8 @@ (set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 9"))]) +;; Expands to: +;; lwp_lwpinssi3, lwp_lwpinsdi3 (define_expand "lwp_lwpins<mode>3" [(set (reg:CCC FLAGS_REG) (unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand" "r") @@ -18983,6 +19744,8 @@ (eq:QI (reg:CCC FLAGS_REG) (const_int 0)))] "TARGET_LWP") +;; Expands to: +;; *lwp_lwpinssi3_1, *lwp_lwpinsdi3_1 (define_insn "*lwp_lwpins<mode>3_1" [(set (reg:CCC FLAGS_REG) (unspec_volatile:CCC [(match_operand:SWI48 0 "register_operand" "r") @@ -19010,6 +19773,8 @@ (UNSPECV_WRFSBASE "fs") (UNSPECV_WRGSBASE "gs")]) +;; Expands to: +;; rdfsbasesi, rdgsbasesi, rdfsbasedi, rdgsbasedi (define_insn "rd<fsgs>base<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec_volatile:SWI48 [(const_int 0)] RDFSGSBASE))] @@ -19018,6 +19783,8 @@ [(set_attr "type" "other") (set_attr "prefix_extra" "2")]) +;; Expands to: +;; wrfsbasesi, wrgsbasesi, wrfsbasedi, wrgsbasedi (define_insn "wr<fsgs>base<mode>" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")] WRFSGSBASE)] @@ -19026,6 +19793,8 @@ [(set_attr "type" "other") (set_attr "prefix_extra" "2")]) +;; Expands to: +;; rdrandhi_1, rdrandsi_1, rdranddi_1 (define_insn "rdrand<mode>_1" [(set (match_operand:SWI248 0 "register_operand" "=r") (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND)) @@ -19036,6 +19805,8 @@ [(set_attr "type" "other") (set_attr "prefix_extra" "1")]) +;; Expands to: +;; rdseedhi_1, rdseedsi_1, rdseeddi_1 (define_insn "rdseed<mode>_1" [(set (match_operand:SWI248 0 "register_operand" "=r") (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDSEED)) @@ -19173,6 +19944,8 @@ "mwaitx" [(set_attr "length" "3")]) +;; Expands to: +;; monitorx_si, monitorx_di (define_insn "monitorx_<mode>" [(unspec_volatile [(match_operand:P 0 "register_operand" "a") (match_operand:SI 1 "register_operand" "c") @@ -19188,6 +19961,8 @@ ;; MPX instructions +;; Expands to: +;; bnd32_mk, bnd64_mk (define_expand "<mode>_mk" [(set (match_operand:BND 0 "register_operand") (unspec:BND @@ -19203,6 +19978,8 @@ UNSPEC_BNDMK_ADDR); }) +;; Expands to: +;; *bnd32_mk, *bnd64_mk (define_insn "*<mode>_mk" [(set (match_operand:BND 0 "register_operand" "=w") (unspec:BND @@ -19216,12 +19993,16 @@ "bndmk\t{%3, %0|%0, %3}" [(set_attr "type" "mpxmk")]) +;; Expands to: +;; movbnd32, movbnd64 (define_expand "mov<mode>" [(set (match_operand:BND 0 "general_operand") (match_operand:BND 1 "general_operand"))] "TARGET_MPX" "ix86_expand_move (<MODE>mode, operands); DONE;") +;; Expands to: +;; *movbnd32_internal_mpx, *movbnd64_internal_mpx (define_insn "*mov<mode>_internal_mpx" [(set (match_operand:BND 0 "nonimmediate_operand" "=w,m") (match_operand:BND 1 "general_operand" "wm,w"))] @@ -19229,6 +20010,8 @@ "bndmov\t{%1, %0|%0, %1}" [(set_attr "type" "mpxmov")]) +;; Expands to: +;; bnd32_cl, bnd32_cu, bnd32_cn, bnd64_cl, bnd64_cu, bnd64_cn (define_expand "<mode>_<bndcheck>" [(parallel [(unspec @@ -19242,6 +20025,8 @@ MEM_VOLATILE_P (operands[2]) = 1; }) +;; Expands to: +;; *bnd32_cl, *bnd32_cu, *bnd32_cn, *bnd64_cl, *bnd64_cu, *bnd64_cn (define_insn "*<mode>_<bndcheck>" [(unspec [(match_operand:BND 0 "register_operand" "w") @@ -19252,6 +20037,8 @@ "bnd<bndcheck>\t{%a1, %0|%0, %a1}" [(set_attr "type" "mpxchk")]) +;; Expands to: +;; bnd32_ldx, bnd64_ldx (define_expand "<mode>_ldx" [(parallel [(set (match_operand:BND 0 "register_operand") @@ -19273,6 +20060,8 @@ UNSPEC_BNDLDX_ADDR); }) +;; Expands to: +;; *bnd32_ldx, *bnd64_ldx (define_insn "*<mode>_ldx" [(set (match_operand:BND 0 "register_operand" "=w") (unspec:BND @@ -19287,6 +20076,8 @@ "bndldx\t{%3, %0|%0, %3}" [(set_attr "type" "mpxld")]) +;; Expands to: +;; bnd32_stx, bnd64_stx (define_expand "<mode>_stx" [(parallel [(unspec @@ -19311,6 +20102,8 @@ MEM_VOLATILE_P (operands[4]) = 1; }) +;; Expands to: +;; *bnd32_stx, *bnd64_stx (define_insn "*<mode>_stx" [(unspec [(match_operator:<bnd_ptr> 3 "bnd_mem_operator" @@ -19326,6 +20119,8 @@ "bndstx\t{%2, %3|%3, %2}" [(set_attr "type" "mpxst")]) +;; Expands to: +;; move_size_reloc_si, move_size_reloc_di (define_insn "move_size_reloc_<mode>" [(set (match_operand:SWI48 0 "register_operand" "=r") (unspec:SWI48

RFD: annotate iterator patterns with expanded forms

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