From patchwork Thu Nov 26 16:00:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Wahab X-Patchwork-Id: 549158 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0CD4D1402C4 for ; Fri, 27 Nov 2015 03:00:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=jM3AeJix; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=b9mL1scUf/+GqCoTh ++Hm8ex8G2LDxMHT4+qgSvxXn8KXrFdQOMrMCbHSXVeAG3rQAnq82iBunQeUxbh9 LqPjFeRdRV46tMkSB1Fs2kZu4kiv4QcrGq6AdaIVAPFlWafRIyB9PHh1dguSOsVG h6yYbFEaod7WQTSkSgMA9K0/CY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=bSGRyGzHwDDSr8/AnrKIbpH dBDQ=; b=jM3AeJixvWXEXwzIopV4nSHGuGEIIDehTre+m4A3UU/6tUlOzHkMsTv 7DTXiOHBMKGGppM0k1u1DcMaJIyS3SU4Pql3Fa1MfDXPub/ipY0KYGUKA3EarCOB APsaMp97sTCDcI77PTXSpJADUBu4EQM1Qi22CkhRAqzJkg44218w= Received: (qmail 92859 invoked by alias); 26 Nov 2015 16:00:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92782 invoked by uid 89); 26 Nov 2015 16:00:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.6 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 26 Nov 2015 16:00:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5B02149 for ; Thu, 26 Nov 2015 08:00:09 -0800 (PST) Received: from e108033-lin.cambridge.arm.com (e108033-lin.cambridge.arm.com [10.2.206.36]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 092123F308 for ; Thu, 26 Nov 2015 08:00:26 -0800 (PST) Subject: [PATCH 3/7][ARM] Add patterns for new instructions To: gcc-patches@gcc.gnu.org References: <56572B79.9000406@foss.arm.com> From: Matthew Wahab Message-ID: <56572C99.6000401@foss.arm.com> Date: Thu, 26 Nov 2015 16:00:25 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <56572B79.9000406@foss.arm.com> X-IsSubscribed: yes Hello, This patch adds patterns for the instructions, vqrdmlah and vqrdmlsh, introduced in the ARMv8.1 architecture. The instructions are made available when -march=armv8.1-a is enabled with suitable fpu settings, such as -mfpu=neon-fp-armv8 -mfloat-abi=hard. Tested the series for arm-none-eabi with cross-compiled check-gcc on an ARMv8.1 emulator. Also tested arm-none-linux-gnueabihf with native bootstrap and make check. Ok for trunk? Matthew gcc/ 2015-11-26 Matthew Wahab * config/arm/iterators.md (VQRDMLH_AS): New. (neon_rdma_as): New. * config/arm/neon.md (neon_vqrdmlh): New. (neon_vqrdmlh_lane): New. * config/arm/unspecs.md (UNSPEC_VQRDMLAH): New. (UNSPEC_VQRDMLSH): New. From fea646491d51548b775fdfb5a4fd6d6bc72d4c83 Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Wed, 17 Jun 2015 12:00:50 +0100 Subject: [PATCH 3/7] [ARM] Add patterns for new instructions. Change-Id: Ia84c345019c7beda2d3c6c39074043d2e005347a --- gcc/config/arm/iterators.md | 5 +++++ gcc/config/arm/neon.md | 45 +++++++++++++++++++++++++++++++++++++++++++++ gcc/config/arm/unspecs.md | 2 ++ 3 files changed, 52 insertions(+) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 6a54125..c7a6880 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -362,6 +362,8 @@ (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) +(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) + ;;---------------------------------------------------------------------------- ;; Mode attributes ;;---------------------------------------------------------------------------- @@ -831,3 +833,6 @@ (simple_return " && use_simple_return_p ()")]) (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") (simple_return " && use_simple_return_p ()")]) + +;; Attributes for VQRDMLAH/VQRDMLSH +(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 62fb6da..844ef5e 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2014,6 +2014,18 @@ [(set_attr "type" "neon_sat_mul_")] ) +;; vqrdmlah, vqrdmlsh +(define_insn "neon_vqrdmlh" + [(set (match_operand:VMDQI 0 "s_register_operand" "=w") + (unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "0") + (match_operand:VMDQI 2 "s_register_operand" "w") + (match_operand:VMDQI 3 "s_register_operand" "w")] + VQRDMLH_AS))] + "TARGET_NEON_RDMA" + "vqrdmlh.\t%0, %2, %3" + [(set_attr "type" "neon_sat_mla__long")] +) + (define_insn "neon_vqdmlal" [(set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") @@ -3176,6 +3188,39 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_sat_mul__scalar_q")] ) +;; vqrdmlah_lane, vqrdmlsh_lane +(define_insn "neon_vqrdmlh_lane" + [(set (match_operand:VMQI 0 "s_register_operand" "=w") + (unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "0") + (match_operand:VMQI 2 "s_register_operand" "w") + (match_operand: 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i")] + VQRDMLH_AS))] + "TARGET_NEON_RDMA" +{ + return + "vqrdmlh.\t%q0, %q2, %P3[%c4]"; +} + [(set_attr "type" "neon_mla__scalar")] +) + +(define_insn "neon_vqrdmlh_lane" + [(set (match_operand:VMDI 0 "s_register_operand" "=w") + (unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" + "") + (match_operand:SI 4 "immediate_operand" "i")] + VQRDMLH_AS))] + "TARGET_NEON_RDMA" +{ + return + "vqrdmlh.\t%P0, %P2, %P3[%c4]"; +} + [(set_attr "type" "neon_mla__scalar")] +) + (define_insn "neon_vmla_lane" [(set (match_operand:VMD 0 "s_register_operand" "=w") (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0") diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 44d4e7d..e7ae9a2 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -360,5 +360,7 @@ UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN + UNSPEC_VQRDMLAH + UNSPEC_VQRDMLSH ]) -- 2.1.4