From patchwork Wed Nov 25 10:10:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Wahab X-Patchwork-Id: 548461 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EE5C9140213 for ; Wed, 25 Nov 2015 21:11:05 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=nSxhxB0E; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=h0iS5ii0cQEyT+UGW D49LAF1KDPg/Qu3eNCbDnk15pt3m/GX2BCiYV42XgYVqJ+oe+dISu6Y8On4YaSzl x5zz3N8KXiVwWYFubtNBOcT8TT4IkLVQTH4a5NmMAXqTFl0X6u0TVOpdfvpT/HEn SGMCi+WeevDNz+o6tX1trmX0TA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=b7WVAW7Z8sjTHE1pTNYCC84 2kIM=; b=nSxhxB0EbvOLmNqlJHb2cOcWPhBHEnItTp3tZ1aoZ2KySVA/ivjyUkC BiuJeVpc7xhvr056b8OaEuyq064GtsCSisflE7t/40+SYR/pzyt7uvfNH2K9To/A nlUw61QJ1AUtc/rEWqGRRzQQQ211RoYphvOYzZaZ1zFzJed3nkrs= Received: (qmail 8243 invoked by alias); 25 Nov 2015 10:10:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8215 invoked by uid 89); 25 Nov 2015 10:10:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 25 Nov 2015 10:10:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AED7849; Wed, 25 Nov 2015 02:10:34 -0800 (PST) Received: from e108033-lin.cambridge.arm.com (e108033-lin.cambridge.arm.com [10.2.206.36]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 040E83F21A; Wed, 25 Nov 2015 02:10:50 -0800 (PST) Subject: Re: [AArch64][dejagnu][PATCH 5/7] Dejagnu support for ARMv8.1 Adv.SIMD. To: James Greenhalgh References: <562A2519.3020102@foss.arm.com> <562A26FA.6070601@foss.arm.com> <562F98F4.7050606@foss.arm.com> <20151123122419.GA11516@arm.com> <565340ED.7080700@foss.arm.com> Cc: Bernhard Reutner-Fischer , gcc-patches@gcc.gnu.org From: Matthew Wahab Message-ID: <56558929.4030204@foss.arm.com> Date: Wed, 25 Nov 2015 10:10:49 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <565340ED.7080700@foss.arm.com> X-IsSubscribed: yes On 23/11/15 16:38, Matthew Wahab wrote: > On 23/11/15 12:24, James Greenhalgh wrote: >> On Tue, Oct 27, 2015 at 03:32:04PM +0000, Matthew Wahab wrote: >>> On 24/10/15 08:16, Bernhard Reutner-Fischer wrote: >>>> On October 23, 2015 2:24:26 PM GMT+02:00, Matthew Wahab >>>> wrote: >>>>> The ARMv8.1 architecture extension adds two Adv.SIMD instructions,. >>>>> This >>>>> patch adds support in Dejagnu for ARMv8.1 Adv.SIMD specifiers and >>>>> checks. >>>>> >>>>> The new test options are >>>>> - { dg-add-options arm_v8_1a_neon }: Add compiler options needed to >>>>> enable ARMv8.1 Adv.SIMD. >>>>> - { dg-require-effective-target arm_v8_1a_neon_hw }: Require a target >>>>> capable of executing ARMv8.1 Adv.SIMD instructions. >>>>> >>> +# Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0 >>> +# otherwise. The test is valid for AArch64. >>> + >>> +proc check_effective_target_arm_v8_1a_neon_hw { } { >>> + if { ![check_effective_target_arm_v8_1a_neon_ok] } { >>> + return 0; >>> + } >>> + return [check_runtime_nocache arm_v8_1a_neon_hw_available { >>> + int >>> + main (void) >>> + { >>> + long long a = 0, b = 1; >>> + long long result = 0; >>> + >>> + asm ("sqrdmlah %s0,%s1,%s2" >>> + : "=w"(result) >>> + : "w"(a), "w"(b) >>> + : /* No clobbers. */); >> >> Hm, those types look wrong, I guess this works but it is an unusual way >> to write it. I presume this is to avoid including arm_neon.h each time, but >> you could just directly use the internal type names for the arm_neon types. >> That is to say __Int32x4_t (or whichever mode you intend to use). >> > > I'll rework the patch to use the internal types names. Attached, the reworked patch which uses internal type __Int32x2_t and cleans up the assembler. Retested aarch64-none-elf with cross-compiled check-gcc on an ARMv8.1 emulator. Also re-ran the cross-compiled gcc.target/aarch64/advsimd-intrinsics tests for aarch64-none-elf on an ARMv8 emulator. Matthew gcc/testsuite 2015-11-24 Matthew Wahab * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): New. (check_effective_target_arm_arch_FUNC_ok) (add_options_for_arm_arch_FUNC) (check_effective_target_arm_arch_FUNC_multilib): Add "armv8.1-a" to the list to be generated. (check_effective_target_arm_v8_1a_neon_ok_nocache): New. (check_effective_target_arm_v8_1a_neon_ok): New. (check_effective_target_arm_v8_1a_neon_hw): New. From 262c24946b2da5833a30b2e3e696bb7ea271059f Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Mon, 26 Oct 2015 14:58:36 +0000 Subject: [PATCH 5/7] [Testsuite] Add dejagnu options for armv8.1 neon Change-Id: Ib58b8c4930ad3971af3ea682eda043e14cd2e8b3 --- gcc/testsuite/lib/target-supports.exp | 57 ++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 3eb46f2..dcd51fd 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2816,6 +2816,16 @@ proc add_options_for_arm_v8_neon { flags } { return "$flags $et_arm_v8_neon_flags -march=armv8-a" } +# Add the options needed for ARMv8.1 Adv.SIMD. + +proc add_options_for_arm_v8_1a_neon { flags } { + if { [istarget aarch64*-*-*] } { + return "$flags -march=armv8.1-a" + } else { + return "$flags" + } +} + proc add_options_for_arm_crc { flags } { if { ! [check_effective_target_arm_crc_ok] } { return "$flags" @@ -3102,7 +3112,8 @@ foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__ v7r "-march=armv7-r" __ARM_ARCH_7R__ v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__ v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__ - v8a "-march=armv8-a" __ARM_ARCH_8A__ } { + v8a "-march=armv8-a" __ARM_ARCH_8A__ + v8_1a "-march=armv8.1a" __ARM_ARCH_8A__ } { eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] { proc check_effective_target_arm_arch_FUNC_ok { } { if { [ string match "*-marm*" "FLAG" ] && @@ -3259,6 +3270,25 @@ proc check_effective_target_arm_neonv2_hw { } { } [add_options_for_arm_neonv2 ""]] } +# Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 +# otherwise. The test is valid for AArch64. + +proc check_effective_target_arm_v8_1a_neon_ok_nocache { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_no_compiler_messages_nocache arm_v8_1a_neon_ok assembly { + #if !defined (__ARM_FEATURE_QRDMX) + #error "__ARM_FEATURE_QRDMX not defined" + #endif + } [add_options_for_arm_v8_1a_neon ""]] +} + +proc check_effective_target_arm_v8_1a_neon_ok { } { + return [check_cached_effective_target arm_v8_1a_neon_ok \ + check_effective_target_arm_v8_1a_neon_ok_nocache] +} + # Return 1 if the target supports executing ARMv8 NEON instructions, 0 # otherwise. @@ -3277,6 +3307,31 @@ proc check_effective_target_arm_v8_neon_hw { } { } [add_options_for_arm_v8_neon ""]] } +# Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0 +# otherwise. The test is valid for AArch64. + +proc check_effective_target_arm_v8_1a_neon_hw { } { + if { ![check_effective_target_arm_v8_1a_neon_ok] } { + return 0; + } + return [check_runtime_nocache arm_v8_1a_neon_hw_available { + int + main (void) + { + __Int32x2_t a = {0, 1}; + __Int32x2_t b = {0, 2}; + __Int32x2_t result; + + asm ("sqrdmlah %0.2s, %1.2s, %2.2s" + : "=w"(result) + : "w"(a), "w"(b) + : /* No clobbers. */); + + return result[0]; + } + } [add_options_for_arm_v8_1a_neon ""]] +} + # Return 1 if this is a ARM target with NEON enabled. proc check_effective_target_arm_neon { } { -- 2.1.4