diff mbox

[AArch64,dejagnu,5/7] Dejagnu support for ARMv8.1 Adv.SIMD.

Message ID 56558929.4030204@foss.arm.com
State New
Headers show

Commit Message

Matthew Wahab Nov. 25, 2015, 10:10 a.m. UTC 
On 23/11/15 16:38, Matthew Wahab wrote:
> On 23/11/15 12:24, James Greenhalgh wrote:
>> On Tue, Oct 27, 2015 at 03:32:04PM +0000, Matthew Wahab wrote:
>>> On 24/10/15 08:16, Bernhard Reutner-Fischer wrote:
>>>> On October 23, 2015 2:24:26 PM GMT+02:00, Matthew Wahab
>>>> <matthew.wahab@foss.arm.com> wrote:
>>>>> The ARMv8.1 architecture extension adds two Adv.SIMD instructions,.
>>>>> This
>>>>> patch adds support in Dejagnu for ARMv8.1 Adv.SIMD specifiers and
>>>>> checks.
>>>>>
>>>>> The new test options are
>>>>> - { dg-add-options arm_v8_1a_neon }: Add compiler options needed to
>>>>>    enable ARMv8.1 Adv.SIMD.
>>>>> - { dg-require-effective-target arm_v8_1a_neon_hw }: Require a target
>>>>>    capable of executing ARMv8.1 Adv.SIMD instructions.
>>>>>

>>> +# Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
>>> +# otherwise.  The test is valid for AArch64.
>>> +
>>> +proc check_effective_target_arm_v8_1a_neon_hw { } {
>>> +    if { ![check_effective_target_arm_v8_1a_neon_ok] } {
>>> +    return 0;
>>> +    }
>>> +    return [check_runtime_nocache arm_v8_1a_neon_hw_available {
>>> +    int
>>> +    main (void)
>>> +    {
>>> +      long long a = 0, b = 1;
>>> +      long long result = 0;
>>> +
>>> +      asm ("sqrdmlah %s0,%s1,%s2"
>>> +           : "=w"(result)
>>> +           : "w"(a), "w"(b)
>>> +           : /* No clobbers.  */);
>>
>> Hm, those types look wrong, I guess this works but it is an unusual way
>> to write it. I presume this is to avoid including arm_neon.h each time, but
>> you could just directly use the internal type names for the arm_neon types.
>> That is to say __Int32x4_t (or whichever mode you intend to use).
>>
>
> I'll rework the patch to use the internal types names.

Attached, the reworked patch which uses internal type __Int32x2_t and
cleans up the assembler.

Retested aarch64-none-elf with cross-compiled check-gcc on an ARMv8.1
emulator. Also re-ran the cross-compiled
gcc.target/aarch64/advsimd-intrinsics tests for aarch64-none-elf on an
ARMv8 emulator.

Matthew

gcc/testsuite
2015-11-24  Matthew Wahab  <matthew.wahab@arm.com>

	* lib/target-supports.exp (add_options_for_arm_v8_1a_neon): New.
	(check_effective_target_arm_arch_FUNC_ok)
	(add_options_for_arm_arch_FUNC)
	(check_effective_target_arm_arch_FUNC_multilib): Add "armv8.1-a"
	to the list to be generated.
	(check_effective_target_arm_v8_1a_neon_ok_nocache): New.
	(check_effective_target_arm_v8_1a_neon_ok): New.
	(check_effective_target_arm_v8_1a_neon_hw): New.

Comments

James Greenhalgh Nov. 25, 2015, 10:56 a.m. UTC | #1 
On Wed, Nov 25, 2015 at 10:10:49AM +0000, Matthew Wahab wrote:
> On 23/11/15 16:38, Matthew Wahab wrote:
> >On 23/11/15 12:24, James Greenhalgh wrote:
> >>On Tue, Oct 27, 2015 at 03:32:04PM +0000, Matthew Wahab wrote:
> >>>On 24/10/15 08:16, Bernhard Reutner-Fischer wrote:
> >>>>On October 23, 2015 2:24:26 PM GMT+02:00, Matthew Wahab
> >>>><matthew.wahab@foss.arm.com> wrote:
> >>>>>The ARMv8.1 architecture extension adds two Adv.SIMD instructions,.
> >>>>>This
> >>>>>patch adds support in Dejagnu for ARMv8.1 Adv.SIMD specifiers and
> >>>>>checks.
> >>>>>
> >>>>>The new test options are
> >>>>>- { dg-add-options arm_v8_1a_neon }: Add compiler options needed to
> >>>>>   enable ARMv8.1 Adv.SIMD.
> >>>>>- { dg-require-effective-target arm_v8_1a_neon_hw }: Require a target
> >>>>>   capable of executing ARMv8.1 Adv.SIMD instructions.
> >>>>>
> 
> >>>+# Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
> >>>+# otherwise.  The test is valid for AArch64.
> >>>+
> >>>+proc check_effective_target_arm_v8_1a_neon_hw { } {
> >>>+    if { ![check_effective_target_arm_v8_1a_neon_ok] } {
> >>>+    return 0;
> >>>+    }
> >>>+    return [check_runtime_nocache arm_v8_1a_neon_hw_available {
> >>>+    int
> >>>+    main (void)
> >>>+    {
> >>>+      long long a = 0, b = 1;
> >>>+      long long result = 0;
> >>>+
> >>>+      asm ("sqrdmlah %s0,%s1,%s2"
> >>>+           : "=w"(result)
> >>>+           : "w"(a), "w"(b)
> >>>+           : /* No clobbers.  */);
> >>
> >>Hm, those types look wrong, I guess this works but it is an unusual way
> >>to write it. I presume this is to avoid including arm_neon.h each time, but
> >>you could just directly use the internal type names for the arm_neon types.
> >>That is to say __Int32x4_t (or whichever mode you intend to use).
> >>
> >
> >I'll rework the patch to use the internal types names.
> 
> Attached, the reworked patch which uses internal type __Int32x2_t and
> cleans up the assembler.
> 
> Retested aarch64-none-elf with cross-compiled check-gcc on an ARMv8.1
> emulator. Also re-ran the cross-compiled
> gcc.target/aarch64/advsimd-intrinsics tests for aarch64-none-elf on an
> ARMv8 emulator.

OK.

Thanks,
James

> gcc/testsuite
> 2015-11-24  Matthew Wahab  <matthew.wahab@arm.com>
> 
> 	* lib/target-supports.exp (add_options_for_arm_v8_1a_neon): New.
> 	(check_effective_target_arm_arch_FUNC_ok)
> 	(add_options_for_arm_arch_FUNC)
> 	(check_effective_target_arm_arch_FUNC_multilib): Add "armv8.1-a"
> 	to the list to be generated.
> 	(check_effective_target_arm_v8_1a_neon_ok_nocache): New.
> 	(check_effective_target_arm_v8_1a_neon_ok): New.
> 	(check_effective_target_arm_v8_1a_neon_hw): New.
diff mbox

Patch

From 262c24946b2da5833a30b2e3e696bb7ea271059f Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 26 Oct 2015 14:58:36 +0000
Subject: [PATCH 5/7] [Testsuite] Add dejagnu options for armv8.1 neon

Change-Id: Ib58b8c4930ad3971af3ea682eda043e14cd2e8b3
---
 gcc/testsuite/lib/target-supports.exp | 57 ++++++++++++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3eb46f2..dcd51fd 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2816,6 +2816,16 @@  proc add_options_for_arm_v8_neon { flags } {
     return "$flags $et_arm_v8_neon_flags -march=armv8-a"
 }
 
+# Add the options needed for ARMv8.1 Adv.SIMD.
+
+proc add_options_for_arm_v8_1a_neon { flags } {
+    if { [istarget aarch64*-*-*] } {
+	return "$flags -march=armv8.1-a"
+    } else {
+	return "$flags"
+    }
+}
+
 proc add_options_for_arm_crc { flags } {
     if { ! [check_effective_target_arm_crc_ok] } {
         return "$flags"
@@ -3102,7 +3112,8 @@  foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__
 				     v7r "-march=armv7-r" __ARM_ARCH_7R__
 				     v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__
 				     v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__
-				     v8a "-march=armv8-a" __ARM_ARCH_8A__ } {
+				     v8a "-march=armv8-a" __ARM_ARCH_8A__
+				     v8_1a "-march=armv8.1a" __ARM_ARCH_8A__ } {
     eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
 	proc check_effective_target_arm_arch_FUNC_ok { } {
 	    if { [ string match "*-marm*" "FLAG" ] &&
@@ -3259,6 +3270,25 @@  proc check_effective_target_arm_neonv2_hw { } {
     } [add_options_for_arm_neonv2 ""]]
 }
 
+# Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
+# otherwise.  The test is valid for AArch64.
+
+proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
+    if { ![istarget aarch64*-*-*] } {
+	return 0
+    }
+    return [check_no_compiler_messages_nocache arm_v8_1a_neon_ok assembly {
+	#if !defined (__ARM_FEATURE_QRDMX)
+	#error "__ARM_FEATURE_QRDMX not defined"
+	#endif
+    } [add_options_for_arm_v8_1a_neon ""]]
+}
+
+proc check_effective_target_arm_v8_1a_neon_ok { } {
+    return [check_cached_effective_target arm_v8_1a_neon_ok \
+		check_effective_target_arm_v8_1a_neon_ok_nocache]
+}
+
 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
 # otherwise.
 
@@ -3277,6 +3307,31 @@  proc check_effective_target_arm_v8_neon_hw { } {
     } [add_options_for_arm_v8_neon ""]]
 }
 
+# Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
+# otherwise.  The test is valid for AArch64.
+
+proc check_effective_target_arm_v8_1a_neon_hw { } {
+    if { ![check_effective_target_arm_v8_1a_neon_ok] } {
+	return 0;
+    }
+    return [check_runtime_nocache arm_v8_1a_neon_hw_available {
+	int
+	main (void)
+	{
+	  __Int32x2_t a = {0, 1};
+	  __Int32x2_t b = {0, 2};
+	  __Int32x2_t result;
+
+	  asm ("sqrdmlah %0.2s, %1.2s, %2.2s"
+	       : "=w"(result)
+	       : "w"(a), "w"(b)
+	       : /* No clobbers.  */);
+
+	  return result[0];
+	}
+    }  [add_options_for_arm_v8_1a_neon ""]]
+}
+
 # Return 1 if this is a ARM target with NEON enabled.
 
 proc check_effective_target_arm_neon { } {
-- 
2.1.4