From patchwork Fri Nov 6 00:09:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evandro Menezes X-Patchwork-Id: 540766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9BFC2140E1A for ; Fri, 6 Nov 2015 11:09:37 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=N0AdB1e7; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=dTrMR6+dQ2dd75VB0 ok4A15H42iTZdl1RX2udwlQFpI5SVSUo63TVxOQ1YVV1E5ULT3gzwwyFYMszSfmf ckf6T/D49QLk3Bx1fCrhC1THHUw8d/Rh32PZbKFSlhT/vbYXj25EKABPJA76S/sI x731B67NSmQvn61tu66ueQ6YHc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:cc:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=2GGq/XZjaKhu/t5xQvK7gNq BlyM=; b=N0AdB1e79+SgkYFiEr23S8W9gzATimwSEp+NW+kHP9W3cgXRRjPlU0f Lzo39nnfWpRGR5+TZ3oBTVtivd6Pu62XBrUWcavv48K1/abn1EJJT6Mw4PF4RVW5 fbSgIymg/4J/7chUR5PK+QGhzn3jSNYv72rha7du9ortl8FIbs7Y= Received: (qmail 55777 invoked by alias); 6 Nov 2015 00:09:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 55763 invoked by uid 89); 6 Nov 2015 00:09:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.6 required=5.0 tests=AWL, BAYES_99, BAYES_999, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: usmailout1.samsung.com Received: from mailout1.w2.samsung.com (HELO usmailout1.samsung.com) (211.189.100.11) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 06 Nov 2015 00:09:26 +0000 Received: from uscpsbgm1.samsung.com (u114.gpu85.samsung.co.kr [203.254.195.114]) by mailout1.w2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NXD004EK9RO1W20@mailout1.w2.samsung.com> for gcc-patches@gcc.gnu.org; Thu, 05 Nov 2015 19:09:24 -0500 (EST) Received: from ussync1.samsung.com ( [203.254.195.81]) by uscpsbgm1.samsung.com (USCPMTA) with SMTP id 73.51.03663.4BFEB365; Thu, 5 Nov 2015 19:09:24 -0500 (EST) Received: from [172.31.207.192] ([105.140.31.209]) by ussync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NXD004HX9RNB350@ussync1.samsung.com>; Thu, 05 Nov 2015 19:09:24 -0500 (EST) Subject: [PATCH 4/4][AArch64] Add cost model for Exynos M1 To: 'gcc-patches' References: <001b01d1110d$0008f890$001ae9b0$@samsung.com> <563A9040.60805@samsung.com> Cc: 'Marcus Shawcroft' , 'James Greenhalgh' , 'Kyrill Tkachov' , Andrew Pinski From: Evandro Menezes Message-id: <563BEFB2.9000308@samsung.com> Date: Thu, 05 Nov 2015 18:09:22 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-version: 1.0 In-reply-to: <563A9040.60805@samsung.com> Content-type: multipart/mixed; boundary=------------070702050809090609010500 X-IsSubscribed: yes 2015-10-25 Evandro Menezes gcc/ * config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model. * config/aarch64/aarch64.c (exynosm1_addrcost_table): New variable. (exynosm1_regmove_cost): Likewise. (exynosm1_vector_cost): Likewise. (exynosm1_tunings): Likewise. * config/arm/aarch-cost-tables.h (exynosm1_extra_costs): Likewise. * config/arm/arm.c (arm_exynos_m1_tune): Likewise. This patch adds the cost model for Exynos M1. This patch depends on a couple of previous patches though, https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00505.html and https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00538.html Please, commit if it's alright. Thank you, From 9b02c57fd2f2507dcc79767d7ffdb7ccec4cdd25 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Thu, 5 Nov 2015 17:58:47 -0600 Subject: [PATCH] [AArch64] Add cost model for Exynos M1 2015-10-25 Evandro Menezes gcc/ * config/aarch64/aarch64-cores.def: Use the Exynos M1 cost model. * config/aarch64/aarch64.c (exynosm1_addrcost_table): New variable. (exynosm1_regmove_cost): Likewise. (exynosm1_vector_cost): Likewise. (exynosm1_tunings): Likewise. * config/arm/aarch-cost-tables.h (exynosm1_extra_costs): Likewise. * config/arm/arm.c (arm_exynos_m1_tune): Likewise. --- gcc/config/aarch64/aarch64-cores.def | 2 +- gcc/config/aarch64/aarch64.c | 66 ++++++++++++++++++++++ gcc/config/arm/aarch-cost-tables.h | 103 +++++++++++++++++++++++++++++++++++ gcc/config/arm/arm-cores.def | 2 +- gcc/config/arm/arm.c | 23 ++++++++ 5 files changed, 194 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index c17baa3..607a333 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -43,7 +43,7 @@ AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03") AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07") AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08") -AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa72, "0x53", "0x001") +AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, "0x53", "0x001") AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1") AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000") diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e7f1c07..d7d3f05 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -215,6 +215,22 @@ static const struct cpu_addrcost_table cortexa57_addrcost_table = 0, /* imm_offset */ }; +static const struct cpu_addrcost_table exynosm1_addrcost_table = +{ + { + 0, /* hi */ + 0, /* si */ + 0, /* di */ + 2, /* ti */ + }, + 0, /* pre_modify */ + 0, /* post_modify */ + 1, /* register_offset */ + 1, /* register_sextend */ + 2, /* register_zextend */ + 0, /* imm_offset */ +}; + static const struct cpu_addrcost_table xgene1_addrcost_table = { { @@ -261,6 +277,16 @@ static const struct cpu_regmove_cost cortexa53_regmove_cost = 2 /* FP2FP */ }; +static const struct cpu_regmove_cost exynosm1_regmove_cost = +{ + 1, /* GP2GP */ + /* Avoid the use of slow int<->fp moves for spilling by setting + their cost higher than memmov_cost (actual, 4 and 9). */ + 9, /* GP2FP */ + 9, /* FP2GP */ + 1 /* FP2FP */ +}; + static const struct cpu_regmove_cost thunderx_regmove_cost = { 2, /* GP2GP */ @@ -313,6 +339,22 @@ static const struct cpu_vector_cost cortexa57_vector_cost = 1 /* cond_not_taken_branch_cost */ }; +static const struct cpu_vector_cost exynosm1_vector_cost = +{ + 1, /* scalar_stmt_cost */ + 5, /* scalar_load_cost */ + 1, /* scalar_store_cost */ + 3, /* vec_stmt_cost */ + 3, /* vec_to_scalar_cost */ + 3, /* scalar_to_vec_cost */ + 5, /* vec_align_load_cost */ + 5, /* vec_unalign_load_cost */ + 1, /* vec_unalign_store_cost */ + 1, /* vec_store_cost */ + 1, /* cond_taken_branch_cost */ + 1 /* cond_not_taken_branch_cost */ +}; + /* Generic costs for vector insn classes. */ static const struct cpu_vector_cost xgene1_vector_cost = { @@ -436,6 +478,30 @@ static const struct tune_params cortexa72_tunings = (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; +static const struct tune_params exynosm1_tunings = +{ + &exynosm1_extra_costs, + &exynosm1_addrcost_table, + &exynosm1_regmove_cost, + &exynosm1_vector_cost, + &generic_branch_cost, + 4, /* memmov_cost */ + 3, /* issue_rate */ + (AARCH64_FUSE_NOTHING), /* fusible_ops */ + 4, /* function_align. */ + 4, /* jump_align. */ + 4, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 48, /* max_case_values. */ + 64, /* cache_line_size. */ + tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ +}; + static const struct tune_params thunderx_tunings = { &thunderx_extra_costs, diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 66e09a8..850bde0 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -331,6 +331,109 @@ const struct cpu_cost_table cortexa57_extra_costs = } }; +const struct cpu_cost_table exynosm1_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + 0, /* shift. */ + COSTS_N_INSNS (0), /* shift_reg. */ + 0, /* arith_shift. */ + COSTS_N_INSNS (1), /* arith_shift_reg. */ + 0, /* log_shift. */ + COSTS_N_INSNS (1), /* log_shift_reg. */ + 0, /* extend. */ + COSTS_N_INSNS (1), /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* rev. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (2), /* simple. */ + COSTS_N_INSNS (3), /* flag_setting. */ + COSTS_N_INSNS (4), /* extend. */ + COSTS_N_INSNS (2), /* add. */ + COSTS_N_INSNS (4), /* extend_add. */ + COSTS_N_INSNS (19) /* idiv. */ + }, + /* MULT DImode */ + { + COSTS_N_INSNS (3), /* simple. */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (4), /* extend. */ + COSTS_N_INSNS (3), /* add. */ + COSTS_N_INSNS (4), /* extend_add. */ + COSTS_N_INSNS (35) /* idiv. */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (3), /* load. */ + COSTS_N_INSNS (4), /* load_sign_extend. */ + COSTS_N_INSNS (3), /* ldrd. */ + COSTS_N_INSNS (2), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 2, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (4), /* loadf. */ + COSTS_N_INSNS (4), /* loadd. */ + COSTS_N_INSNS (4), /* load_unaligned. */ + 0, /* store. */ + 0, /* strd. */ + 0, /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 2, /* stm_regs_per_insn_subsequent. */ + 0, /* storef. */ + 0, /* stored. */ + 0, /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (21), /* div. */ + COSTS_N_INSNS (3), /* mult. */ + COSTS_N_INSNS (4), /* mult_addsub. */ + COSTS_N_INSNS (4), /* fma. */ + COSTS_N_INSNS (2), /* addsub. */ + COSTS_N_INSNS (0), /* fpconst. */ + COSTS_N_INSNS (0), /* neg. */ + COSTS_N_INSNS (3), /* compare. */ + COSTS_N_INSNS (2), /* widen. */ + COSTS_N_INSNS (2), /* narrow. */ + COSTS_N_INSNS (12), /* toint. */ + COSTS_N_INSNS (7), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (34), /* div. */ + COSTS_N_INSNS (3), /* mult. */ + COSTS_N_INSNS (4), /* mult_addsub. */ + COSTS_N_INSNS (4), /* fma. */ + COSTS_N_INSNS (2), /* addsub. */ + COSTS_N_INSNS (0), /* fpconst. */ + COSTS_N_INSNS (0), /* neg. */ + COSTS_N_INSNS (3), /* compare. */ + COSTS_N_INSNS (2), /* widen. */ + COSTS_N_INSNS (2), /* narrow. */ + COSTS_N_INSNS (12), /* toint. */ + COSTS_N_INSNS (7), /* fromint. */ + COSTS_N_INSNS (2) /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (0) /* alu. */ + } +}; + const struct cpu_cost_table xgene1_extra_costs = { /* ALU */ diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 3448e82..18936f0 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -168,7 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_ ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) -ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) +ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1) /* V8 big.LITTLE implementations */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 4310638..6d5a64e 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1991,6 +1991,29 @@ const struct tune_params arm_cortex_a57_tune = tune_params::SCHED_AUTOPREF_FULL }; +const struct tune_params arm_exynos_m1_tune = +{ + arm_9e_rtx_costs, + &exynosm1_extra_costs, + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 3, /* Issue rate. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE, /* Thumb. */ + tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF +}; + const struct tune_params arm_xgene1_tune = { arm_9e_rtx_costs, -- 2.1.0.243.g30d45f7