| Message ID | 562FC0B8.6040607@arm.com |
|---|---|
| State | New |
| Headers | show |
On Tue, Oct 27, 2015 at 06:21:44PM +0000, Kyrill Tkachov wrote: > Hi all, > > The testcase gcc.target/aarch64/vldN_lane_1.c ICEs on aarch64 targets when > RTL checking is enabled. We end up taking the UINTVAL of a CONST_DOUBLE in > aarch64_output_simd_mov_immediate. This is because > aarch64_output_simd_mov_immediate only handles SF and DF inner modes whereas > in that testcase it ends up being passed a V4HF immediate. > > This patch generalises the check and allows for any FP inner mode. > The testcase now compiles successfully with RTL checking enabled. > There are some other RTL checking failures that have been reported in the > last few days and I'll tackle them as I go along. > > Bootstrapped and tested on aarch64. > > Ok for trunk? OK. Thanks, James > > Thanks, > Kyrill > > 2015-10-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> > > * config/aarch64/aarch64.c (aarch64_output_simd_mov_immediate): > Handle floating point inner modes properly.
commit a1714f9da4b4adef0ee2c83cf785b4216725b2fa
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Tue Oct 27 10:27:23 2015 +0000
[AArch64] Handle vector float modes properly in aarch64_output_simd_mov_immediate
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index f4451f9..771b2cf 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -11432,9 +11432,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
lane_count = width / info.element_width;
mode = GET_MODE_INNER (mode);
- if (mode == SFmode || mode == DFmode)
+ if (GET_MODE_CLASS (mode) == MODE_FLOAT)
{
gcc_assert (info.shift == 0 && ! info.mvn);
+ /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
+ move immediate path. */
if (aarch64_float_const_zero_rtx_p (info.value))
info.value = GEN_INT (0);
else
@@ -11458,6 +11460,7 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
mnemonic = info.mvn ? "mvni" : "movi";
shift_op = info.msl ? "msl" : "lsl";
+ gcc_assert (CONST_INT_P (info.value));
if (lane_count == 1)
snprintf (templ, sizeof (templ), "%s\t%%d0, " HOST_WIDE_INT_PRINT_HEX,
mnemonic, UINTVAL (info.value));
Hi all, The testcase gcc.target/aarch64/vldN_lane_1.c ICEs on aarch64 targets when RTL checking is enabled. We end up taking the UINTVAL of a CONST_DOUBLE in aarch64_output_simd_mov_immediate. This is because aarch64_output_simd_mov_immediate only handles SF and DF inner modes whereas in that testcase it ends up being passed a V4HF immediate. This patch generalises the check and allows for any FP inner mode. The testcase now compiles successfully with RTL checking enabled. There are some other RTL checking failures that have been reported in the last few days and I'll tackle them as I go along. Bootstrapped and tested on aarch64. Ok for trunk? Thanks, Kyrill 2015-10-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/aarch64/aarch64.c (aarch64_output_simd_mov_immediate): Handle floating point inner modes properly.