From 4e7a33c81b2435765b661c189171f2ce9a65c5ac Mon Sep 17 00:00:00 2001
From: Mikhail Maltsev <maltsevm@gmail.com>
Date: Sun, 4 Oct 2015 22:51:03 +0300
Subject: [PATCH 8/9] Target-related parts
---
gcc/config/alpha/alpha.c | 4 +---
gcc/config/arm/arm.c | 2 +-
gcc/config/bfin/bfin.c | 4 +---
gcc/config/i386/i386.c | 9 ++++-----
gcc/config/ia64/ia64.c | 20 +++++++++-----------
gcc/config/m68k/m68k.c | 2 +-
gcc/config/rs6000/rs6000.c | 14 ++++++--------
gcc/config/rs6000/rs6000.h | 2 +-
gcc/config/visium/visium.c | 2 +-
9 files changed, 25 insertions(+), 34 deletions(-)
@@ -5574,11 +5574,9 @@ alpha_function_arg (cumulative_args_t cum_v, machine_mode mode,
basereg = 16;
else
{
-#ifdef ENABLE_CHECKING
/* With alpha_split_complex_arg, we shouldn't see any raw complex
values here. */
- gcc_assert (!COMPLEX_MODE_P (mode));
-#endif
+ gcc_checking_assert (!COMPLEX_MODE_P (mode));
/* Set up defaults for FP operands passed in FP registers, and
integral operands passed in integer registers. */
@@ -26854,7 +26854,7 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
else
asm_fprintf (asm_out_file, "%r", reg);
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
/* Check that the addresses are consecutive. */
e = XEXP (SET_DEST (e), 0);
if (GET_CODE (e) == PLUS)
@@ -3811,8 +3811,7 @@ hwloop_optimize (hwloop_info loop)
edge e;
edge_iterator ei;
-#ifdef ENABLE_CHECKING
- if (loop->head != loop->incoming_dest)
+ if (CHECKING_P && loop->head != loop->incoming_dest)
{
/* We aren't entering the loop at the top. Since we've established
that the loop is entered only at one point, this means there
@@ -3822,7 +3821,6 @@ hwloop_optimize (hwloop_info loop)
FOR_EACH_EDGE (e, ei, loop->head->preds)
gcc_assert (!(e->flags & EDGE_FALLTHRU));
}
-#endif
emit_insn_before (seq, BB_HEAD (loop->head));
seq = emit_label_before (gen_label_rtx (), seq);
@@ -17209,7 +17209,7 @@ ix86_print_operand_address (FILE *file, rtx addr)
/* Print SImode register names to force addr32 prefix. */
if (SImode_address_operand (addr, VOIDmode))
{
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
gcc_assert (TARGET_64BIT);
switch (GET_CODE (addr))
{
@@ -17481,10 +17481,10 @@ output_387_binary_op (rtx insn, rtx *operands)
const char *ssep;
int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
-#ifdef ENABLE_CHECKING
/* Even if we do not want to check the inputs, this documents input
constraints. Which helps in understanding the following code. */
- if (STACK_REG_P (operands[0])
+ if (CHECKING_P
+ && STACK_REG_P (operands[0])
&& ((REG_P (operands[1])
&& REGNO (operands[0]) == REGNO (operands[1])
&& (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
@@ -17494,8 +17494,7 @@ output_387_binary_op (rtx insn, rtx *operands)
&& (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
; /* ok */
else
- gcc_assert (is_sse);
-#endif
+ gcc_checking_assert (is_sse);
switch (GET_CODE (operands[3]))
{
@@ -6145,7 +6145,7 @@ struct reg_write_state
/* Cumulative info for the current instruction group. */
struct reg_write_state rws_sum[NUM_REGS];
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
/* Bitmap whether a register has been written in the current insn. */
HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
/ HOST_BITS_PER_WIDEST_FAST_INT];
@@ -7313,15 +7313,13 @@ ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
int sched_verbose ATTRIBUTE_UNUSED,
int max_ready ATTRIBUTE_UNUSED)
{
-#ifdef ENABLE_CHECKING
- rtx_insn *insn;
-
- if (!sel_sched_p () && reload_completed)
- for (insn = NEXT_INSN (current_sched_info->prev_head);
- insn != current_sched_info->next_tail;
- insn = NEXT_INSN (insn))
- gcc_assert (!SCHED_GROUP_P (insn));
-#endif
+ if (CHECKING_P && !sel_sched_p () && reload_completed)
+ {
+ for (rtx_insn *insn = NEXT_INSN (current_sched_info->prev_head);
+ insn != current_sched_info->next_tail;
+ insn = NEXT_INSN (insn))
+ gcc_assert (!SCHED_GROUP_P (insn));
+ }
last_scheduled_insn = NULL;
init_insn_group_barriers ();
@@ -9319,7 +9317,7 @@ bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail)
}
}
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
{
/* Assert right calculation of middle_bundle_stops. */
int num = best_state->middle_bundle_stops;
@@ -6125,7 +6125,7 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
int sched_verbose ATTRIBUTE_UNUSED,
int n_insns ATTRIBUTE_UNUSED)
{
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
/* Check that all instructions have DFA reservations and
that all instructions can be issued from a clean state. */
{
@@ -12884,15 +12884,13 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp)
case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
op[nopnds++] = GEN_INT (1);
-#ifdef ENABLE_CHECKING
- attr |= RS6000_BTC_UNARY;
-#endif
+ if (CHECKING_P)
+ attr |= RS6000_BTC_UNARY;
break;
case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
op[nopnds++] = GEN_INT (0);
-#ifdef ENABLE_CHECKING
- attr |= RS6000_BTC_UNARY;
-#endif
+ if (CHECKING_P)
+ attr |= RS6000_BTC_UNARY;
break;
default:
break;
@@ -12913,7 +12911,7 @@ htm_expand_builtin (tree exp, rtx target, bool * expandedp)
op[nopnds++] = cr;
}
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
int expected_nopnds = 0;
if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
expected_nopnds = 1;
@@ -24097,7 +24095,7 @@ rs6000_emit_prologue (void)
prior to it, when r12 is not used here for other purposes. */
rtx_insn *sp_adjust = 0;
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
/* Track and check usage of r0, r11, r12. */
int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
#define START_USE(R) do \
@@ -1471,7 +1471,7 @@ enum reg_class
extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
-#if ENABLE_CHECKING
+#if CHECKING_P
#define REGNO_REG_CLASS(REGNO) \
(gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
rs6000_regno_regclass[(REGNO)])
@@ -1345,7 +1345,7 @@ visium_setup_incoming_varargs (cumulative_args_t pcum_v,
local_args_so_far.p = &local_copy;
locargs = get_cumulative_args (pcum_v);
-#ifdef ENABLE_CHECKING
+#if CHECKING_P
local_args_so_far.magic = CUMULATIVE_ARGS_MAGIC;
#endif
--
2.1.4