diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index afc071f..2228667 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -82,9 +82,6 @@ (define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
   "General purpose register if 64-bit instructions are enabled or NO_REGS.")
 
-(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
-  "VSX vector register to hold scalar double values or NO_REGS.")
-
 (define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
   "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 767721f..87f8bdf 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2514,7 +2514,6 @@ rs6000_debug_reg_global (void)
 	   "wp reg_class = %s\n"
 	   "wq reg_class = %s\n"
 	   "wr reg_class = %s\n"
-	   "ws reg_class = %s\n"
 	   "ww reg_class = %s\n"
 	   "wx reg_class = %s\n"
 	   "wA reg_class = %s\n"
@@ -2529,7 +2528,6 @@ rs6000_debug_reg_global (void)
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -3144,7 +3142,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 	wf - Preferred register class for V4SFmode.
 	wn - always NO_REGS.
 	wr - GPR if 64-bit mode is permitted.
-	ws - Register class to do ISA 2.06 DF operations.
 	ww - Register class to do SF conversions in with VSX operations.
 	wx - Float register if we can do 32-bit int stores.  */
 
@@ -3159,7 +3156,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
       rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
       rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;	/* V2DFmode  */
       rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;	/* V4SFmode  */
-      rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;	/* DFmode  */
     }
 
   /* Add conditional constraints based on various options, to allow us to
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index c91854a..c7fd7a2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1262,7 +1262,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wp,		/* VSX reg for IEEE 128-bit fp TFmode. */
   RS6000_CONSTRAINT_wq,		/* VSX reg for IEEE 128-bit fp KFmode.  */
   RS6000_CONSTRAINT_wr,		/* GPR register if 64-bit  */
-  RS6000_CONSTRAINT_ws,		/* VSX register for DF */
   RS6000_CONSTRAINT_ww,		/* FP or VSX register for vsx float ops.  */
   RS6000_CONSTRAINT_wx,		/* FPR register for STFIWX */
   RS6000_CONSTRAINT_wA,		/* BASE_REGS if 64-bit.  */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 45e0347..a0628c1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -469,10 +469,10 @@ (define_mode_attr zero_fp [(SF "j")
 			   (TD "wn")])
 
 ; Definitions for 64-bit VSX
-(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
+(define_mode_attr f64_vsx [(DF "wa") (DD "wn")])
 
 ; Definitions for 64-bit direct move
-(define_mode_attr f64_dm  [(DF "ws") (DD "d")])
+(define_mode_attr f64_dm  [(DF "wa") (DD "d")])
 
 ; Definitions for 64-bit use of altivec registers
 (define_mode_attr f64_av  [(DF "v") (DD "wn")])
@@ -526,12 +526,12 @@ (define_mode_attr Ff		[(SF "f") (DF "d") (DI "d")])
 ; ISA 2.06 (power7).  This includes instructions that normally target DF mode,
 ; but are used on SFmode, since internally SFmode values are kept in the DFmode
 ; format.
-(define_mode_attr Fv		[(SF "ww") (DF "ws") (DI "wa")])
+(define_mode_attr Fv		[(SF "ww") (DF "wa") (DI "wa")])
 
 ; SF/DF constraint for arithmetic on VSX registers.  This is intended to be
 ; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
 ; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2		[(SF "wa") (DF "ws") (DI "wa")])
+(define_mode_attr Fv2		[(SF "wa") (DF "wa") (DI "wa")])
 
 ; Which isa is needed for those float instructions?
 (define_mode_attr Fisa		[(SF "p8v")  (DF "*") (DI "*")])
@@ -626,7 +626,7 @@ (define_mode_attr ptrm [(SI "m")
 			(DI "Y")])
 
 (define_mode_attr rreg [(SF   "f")
-			(DF   "ws")
+			(DF   "wa")
 			(TF   "f")
 			(TD   "f")
 			(V4SF "wf")
@@ -4783,7 +4783,7 @@ (define_expand "extendsfdf2"
 })
 
 (define_insn_and_split "*extendsfdf2_fpr"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wa,?wa,wa,v")
 	(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wa,Z,wY")))]
   "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
   "@
@@ -4804,7 +4804,7 @@ (define_insn_and_split "*extendsfdf2_fpr"
    (set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
 
 (define_insn "*extendsfdf2_snan"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wa")))]
   "TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
   "@
@@ -4821,7 +4821,7 @@ (define_expand "truncdfsf2"
 
 (define_insn "*truncdfsf2_fpr"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
-	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
+	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT"
   "@
    frsp %0,%1
@@ -6027,8 +6027,8 @@ (define_insn "fctiwuz_<mode>"
 ;; since the friz instruction does not truncate the value if the floating
 ;; point value is < LONG_MIN or > LONG_MAX.
 (define_insn "*friz"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
-	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
+	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
   "TARGET_HARD_FLOAT && TARGET_FPRND
    && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
@@ -6223,7 +6223,7 @@ (define_expand "floatsisf2"
 })
 
 (define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_FCFID && TARGET_HARD_FLOAT"
   "@
@@ -6237,7 +6237,7 @@ (define_insn "floatdidf2"
 ; hit.  We will split after reload to avoid the trip through the GPRs
 
 (define_insn_and_split "*floatdidf2_mem"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && TARGET_FCFID"
@@ -6257,7 +6257,7 @@ (define_expand "floatunsdidf2"
   "")
 
 (define_insn "*floatunsdidf2_fcfidu"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && TARGET_FCFIDU"
   "@
@@ -6266,7 +6266,7 @@ (define_insn "*floatunsdidf2_fcfidu"
   [(set_attr "type" "fp")])
 
 (define_insn_and_split "*floatunsdidf2_mem"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
    (clobber (match_scratch:DI 2 "=d,wa"))]
   "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
@@ -7855,7 +7855,7 @@ (define_insn_and_split "extenddf<mode>2_fprs"
 (define_insn_and_split "extenddf<mode>2_vsx"
   [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
 	(float_extend:IBM128
-	 (match_operand:DF 1 "nonimmediate_operand" "ws,m")))]
+	 (match_operand:DF 1 "nonimmediate_operand" "wa,m")))]
   "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
   "#"
   "&& reload_completed"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bc12158..57f9963 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -115,7 +115,7 @@ (define_mode_attr VSr	[(V16QI "v")
 			 (V2DI  "wd")
 			 (V2DF  "wd")
 			 (DI	"wa")
-			 (DF    "ws")
+			 (DF    "wa")
 			 (SF	"ww")
 			 (TF	"wp")
 			 (KF	"wq")
@@ -127,7 +127,7 @@ (define_mode_attr VSr	[(V16QI "v")
 ;; hold the data
 (define_mode_attr VSr2	[(V2DF  "wd")
 			 (V4SF  "wf")
-			 (DF    "ws")
+			 (DF    "wa")
 			 (SF	"ww")
 			 (DI	"wa")
 			 (KF	"wq")
@@ -135,20 +135,20 @@ (define_mode_attr VSr2	[(V2DF  "wd")
 
 (define_mode_attr VSr3	[(V2DF  "wa")
 			 (V4SF  "wa")
-			 (DF    "ws")
+			 (DF    "wa")
 			 (SF	"ww")
 			 (DI	"wa")
 			 (KF	"wq")
 			 (TF	"wp")])
 
 ;; Map the register class for sp<->dp float conversions, destination
-(define_mode_attr VSr4	[(SF	"ws")
+(define_mode_attr VSr4	[(SF	"wa")
 			 (DF	"f")
 			 (V2DF  "wd")
 			 (V4SF	"v")])
 
 ;; Map the register class for sp<->dp float conversions, source
-(define_mode_attr VSr5	[(SF	"ws")
+(define_mode_attr VSr5	[(SF	"wa")
 			 (DF	"f")
 			 (V2DF  "v")
 			 (V4SF	"wd")])
@@ -163,7 +163,7 @@ (define_mode_attr VSa	[(V16QI "wa")
 			 (V2DI  "wa")
 			 (V2DF  "wa")
 			 (DI	"wa")
-			 (DF    "ws")
+			 (DF    "wa")
 			 (SF	"ww")
 			 (V1TI	"wa")
 			 (TI    "wa")
@@ -277,7 +277,7 @@ (define_mode_attr VS_double [(V4SI	"V8SI")
 
 ;; Map register class for 64-bit element in 128-bit vector for normal register
 ;; to register moves
-(define_mode_attr VS_64reg [(V2DF	"ws")
+(define_mode_attr VS_64reg [(V2DF	"wa")
 			    (V2DI	"wa")])
 
 ;; Iterators for loading constants with xxspltib
@@ -2199,7 +2199,7 @@ (define_insn "vsx_<VS_spdp_insn>"
 
 ;; xscvspdp, represent the scalar SF type as V4SF
 (define_insn "vsx_xscvspdp"
-  [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+  [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
 		   UNSPEC_VSX_CVSPDP))]
   "VECTOR_UNIT_VSX_P (V4SFmode)"
@@ -2237,14 +2237,14 @@ (define_insn "vsx_xscvdpsp_scalar"
 ;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
 (define_insn "vsx_xscvdpspn"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww")
-	(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "ws")]
+	(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wa")]
 		     UNSPEC_VSX_CVDPSPN))]
   "TARGET_XSCVDPSPN"
   "xscvdpspn %x0,%x1"
   [(set_attr "type" "fp")])
 
 (define_insn "vsx_xscvspdpn"
-  [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+  [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
 		   UNSPEC_VSX_CVSPDPN))]
   "TARGET_XSCVSPDPN"
@@ -2453,7 +2453,7 @@ (define_insn "vsx_xvcvsxwdp"
   [(set_attr "type" "vecdouble")])
 
 (define_insn "vsx_xvcvsxwdp_df"
-  [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+  [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
 		   UNSPEC_VSX_CVSXWDP))]
   "TARGET_VSX"
@@ -2469,7 +2469,7 @@ (define_insn "vsx_xvcvuxwdp"
   [(set_attr "type" "vecdouble")])
 
 (define_insn "vsx_xvcvuxwdp_df"
-  [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+  [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
 		   UNSPEC_VSX_CVUXWDP))]
   "TARGET_VSX"
@@ -3771,7 +3771,7 @@ (define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
 ;; Optimize double d = (double) vec_extract (vi, <n>)
 ;; Get the element into the top position and use XVCVSWDP/XVCVUWDP
 (define_insn_and_split "*vsx_extract_si_<uns>float_df"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "=ws")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
 	(any_float:DF
 	 (vec_select:SI
 	  (match_operand:V4SI 1 "gpc_reg_operand" "v")
@@ -3818,7 +3818,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>"
 	  (match_operand:V4SI 1 "gpc_reg_operand" "v")
 	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
    (clobber (match_scratch:V4SI 3 "=v"))
-   (clobber (match_scratch:DF 4 "=ws"))]
+   (clobber (match_scratch:DF 4 "=wa"))]
   "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& 1"
@@ -4350,7 +4350,7 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
 ;; to the top element of the V2DF array without doing an extract.
 
 (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
-  [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws")
+  [(set (match_operand:DF 0 "vfloat_operand" "=&wa,&?wa,wa,?wa")
 	(vec_select:DF
 	 (VEC_reduc:V2DF
 	  (vec_concat:V2DF
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0fbe332..b0a7454 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
 
 When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
-@code{wp}, @code{wq}, @code{ws}, or @code{ww})
+@code{wp}, @code{wq}, or @code{ww})
 that take VSX registers, you must use @code{%x<n>} in the template so
 that the correct register is used.  Otherwise the register number
 output in the assembly file will be incorrect if an Altivec register
@@ -3266,9 +3266,6 @@ VSX register to use for IEEE 128-bit floating point, or NO_REGS.
 @item wr
 General purpose register if 64-bit instructions are enabled or NO_REGS.
 
-@item ws
-VSX vector register to hold scalar double values or NO_REGS.
-
 @item ww
 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
 
