| Message ID | 55C23E00.2070109@arm.com |
|---|---|
| State | New |
| Headers | show |
On 5 August 2015 at 17:46, Renlin Li <renlin.li@arm.com> wrote: > Hi Kyrill, > > > On 30/07/15 17:08, Kyrill Tkachov wrote: >> >> Hi Renlin, >> >> On 30/07/15 16:50, Renlin Li wrote: >>> >>> Hi all, >>> >>> This insn should match the following similar rtx pattern and remove the >>> redundant zero_extend operation if the width of zero_extract and >>> inner-size of zero_extend totally match. >>> >>> (set (zero_extract:SI (reg/i:SI 0 x0) >>> (const_int 8 [0x8]) >>> (const_int 0 [0])) >>> (zero_extend:SI (reg:QI 1 x1 [ y ]))) >>> >>> >>> aarch64-none-elf regression tests Okay. Okay to commit? >>> >>> Regards, >>> Renlin >>> >>> gcc/ChangeLog: >>> >>> 2015-07-30 Renlin Li <renlin.li@arm.com> >>> >>> * config/aarch64/aarch64.md (combine_bfi): New pattern. >>> >>> gcc/testsuite/ChangeLog: >>> >>> 2015-07-30 Renlin Li <renlin.li@arm.com> >>> >>> * gcc.target/aarch64/combine-bfi.c: New. >> >> +(define_insn "*combine_bfi<GPI:mode><ALLX:mode>" >> + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") >> + (match_operand 1 "const_int_operand" "n") >> + (match_operand 2 "const_int_operand" "n")) >> + (zero_extend:GPI (match_operand:ALLX 3 "register_operand" "r")))] >> + "UINTVAL (operands[1]) == <ALLX:sizen>" >> + "bfi\\t%<w>0, %<w>3, %2, %1" >> + [(set_attr "type" "bfm")] >> +) >> >> I notice we don't have any other patterns in aarch64 that start with >> combine_*. >> Would it be better to name them something like >> "*aarch64_bfi<GPI:mode><ALLX:mode>4" instead? > > Thanks for the suggestion. I have adjust the patch accordingly. > > Regards, > Renlin > > > > gcc/ChangeLog: > > 2015-08-05 Renlin Li <renlin.li@arm.com> > > * config/aarch64/aarch64.md > (*aarch64_bfi<GPI:mode><ALLX:mode>4): New pattern. > > gcc/testsuite/ChangeLog: > > 2015-08-05 Renlin Li <renlin.li@arm.com> > > * gcc.target/aarch64/combine-bfi.c: New. For new test cases in this directory, follow the guidance given on the wiki here https://gcc.gnu.org/wiki/TestCaseWriting, specifically add the suffix _N, hence combine_bfi_1.c OK with that change. /Marcus
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1dbadc0..858fe77 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3903,6 +3903,16 @@ [(set_attr "type" "bfm")] ) +(define_insn "*aarch64_bfi<GPI:mode><ALLX:mode>4" + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") + (match_operand 1 "const_int_operand" "n") + (match_operand 2 "const_int_operand" "n")) + (zero_extend:GPI (match_operand:ALLX 3 "register_operand" "r")))] + "UINTVAL (operands[1]) == <ALLX:sizen>" + "bfi\\t%<w>0, %<w>3, %2, %1" + [(set_attr "type" "bfm")] +) + (define_insn "*extr_insv_lower_reg<mode>" [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") (match_operand 1 "const_int_operand" "n") diff --git a/gcc/testsuite/gcc.target/aarch64/combine-bfi.c b/gcc/testsuite/gcc.target/aarch64/combine-bfi.c new file mode 100644 index 0000000..06331f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/combine-bfi.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-combine" } */ + +int +f1 (int x, int y) +{ + return (x & ~0x0ffff00) | ((y << 8) & 0x0ffff00); +} + +int +f2 (int x, int y) +{ + return (x & ~0x0ff000) | ((y & 0x0ff) << 12); +} + +int +f3 (int x, int y) +{ + return (x & ~0xffff) | (y & 0xffff); +} + +int +f4 (int x, int y) +{ + return (x & ~0xff) | (y & 0xff); +} + +long +f5 (long x, long y) +{ + return (x & ~0xffffffffull) | (y & 0xffffffff); +} + +/* { dg-final { scan-rtl-dump-times "\\*aarch64_bfi" 5 "combine" } } */