From patchwork Tue May 12 16:44:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 471409 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4ECDF140D18 for ; Wed, 13 May 2015 02:45:05 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=UGp4N8UC; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=It3wmbJuTagF0AoVhxXqsthiG4VkKSW8AEdBns0KQgYu4n Gjhcf3Rdr4xcNn+Bm78GTX6RzmEkq/iNTV28VRTlvU+TnD3lDQr/UIa/+daCigb6 IPFrDlWVJdf6ro919vAPuuj+a8ihZN7S8Bf/PIRiEAmdTjxuHYxWahcWNAXLo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=tjmYwkj1bPNJTYx5+WY1sD2h+RA=; b=UGp4N8UCah1HJ3jglGWU ELghnLQzauWckf4kBF6AQb2vprd9m4yC28RAADiimoxXbjeMLdLGeOT5soA9Uw52 4xC2/NM4HmF41bscoJeTHYqGHT7eWQkYa3UhnSwQTt5dzlWAfAfTYbjL7bqGcDSq G3G41QNaUS+oRa+OMGaGUWk= Received: (qmail 98942 invoked by alias); 12 May 2015 16:44:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 98922 invoked by uid 89); 12 May 2015 16:44:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.0 required=5.0 tests=AWL, BAYES_20, KAM_LAZY_DOMAIN_SECURITY, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 May 2015 16:44:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 420C629 for ; Tue, 12 May 2015 09:44:10 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8B4413F21B; Tue, 12 May 2015 09:44:46 -0700 (PDT) Message-ID: <55522DFC.2040001@foss.arm.com> Date: Tue, 12 May 2015 17:44:44 +0100 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: gcc-patches Subject: [PATCH, ARM] Make tune params tables more self-documenting X-IsSubscribed: yes This patch modifies the way that the tune_params data structures are constructed so that: 1) The initializers are (mostly) self documenting. 2) The compiler does a better job of detecting merge failures. Mostly this resolves around using C++ enums, such that we get type clashes if elements do not match up correctly (especially the last element). Tested on arm-eabi and applied to trunk. * arm-protos.h (arm_sched_autopref): Delete. (tune_params): Re-organize, use enums for flag values. (FUSE_OPS): New macro. * arm.c (ARM_PREFETCH_NOT_BENEFICIAL): Update. (ARM_PREFETCH_BENEFICIAL): Likewise. (ARM_FUSE_NOTHING, ARM_FUSE_MOVW_MOVT): Delete. (arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune) (arm_xscale_tune, arm_9e_tune, arm_marvell_pj4_tune) (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune) (arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune) (arm_cortex_a57_tune, arm_xgene1_tune, arm_cortex_a5_tune) (arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune) (arm_cortex_m7_tune, arm_v6m_tune, arm_fa726te_tune): Use new format. (arm_option_override, thumb2_reorg, arm_print_tune_info) (aarch_macro_fusion_pair_p): Update uses of current_tune. * arm.h (LOGCIAL_OP_NON_SHORT_CIRCUIT): Likewise. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index bda20ca..b632a77 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -251,13 +251,6 @@ struct cpu_vec_costs { struct cpu_cost_table; -enum arm_sched_autopref - { - ARM_SCHED_AUTOPREF_OFF, - ARM_SCHED_AUTOPREF_RANK, - ARM_SCHED_AUTOPREF_FULL - }; - /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this structure is modified. */ @@ -266,41 +259,57 @@ struct tune_params bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); const struct cpu_cost_table *insn_extra_cost; bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *); + int (*branch_cost) (bool, bool); + /* Vectorizer costs. */ + const struct cpu_vec_costs* vec_costs; int constant_limit; /* Maximum number of instructions to conditionalise. */ int max_insns_skipped; - int num_prefetch_slots; - int l1_cache_size; - int l1_cache_line_size; - bool prefer_constant_pool; - int (*branch_cost) (bool, bool); + /* Maximum number of instructions to inline calls to memset. */ + int max_insns_inline_memset; + /* Issue rate of the processor. */ + unsigned int issue_rate; + /* Explicit prefetch data. */ + struct + { + int num_slots; + int l1_cache_size; + int l1_cache_line_size; + } prefetch; + enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE} + prefer_constant_pool: 1; /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */ - bool prefer_ldrd_strd; + enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1; /* The preference for non short cirtcuit operation when optimizing for performance. The first element covers Thumb state and the second one is for ARM state. */ - bool logical_op_non_short_circuit[2]; - /* Vectorizer costs. */ - const struct cpu_vec_costs* vec_costs; - /* Prefer Neon for 64-bit bitops. */ - bool prefer_neon_for_64bits; + enum log_op_non_sc {LOG_OP_NON_SC_FALSE, LOG_OP_NON_SC_TRUE}; + log_op_non_sc logical_op_non_short_circuit_thumb: 1; + log_op_non_sc logical_op_non_short_circuit_arm: 1; /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */ - bool disparage_flag_setting_t16_encodings; - /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags - would be set. */ - bool disparage_partial_flag_setting_t16_encodings; + enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL} + disparage_flag_setting_t16_encodings: 2; + enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1; /* Prefer to inline string operations like memset by using Neon. */ - bool string_ops_prefer_neon; - /* Maximum number of instructions to inline calls to memset. */ - int max_insns_inline_memset; - /* Bitfield encoding the fuseable pairs of instructions. */ - unsigned int fuseable_ops; + enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE} + string_ops_prefer_neon: 1; + /* Bitfield encoding the fuseable pairs of instructions. Use FUSE_OPS + in an initializer if multiple fusion operations are supported on a + target. */ + enum fuse_ops + { + FUSE_NOTHING = 0, + FUSE_MOVW_MOVT = 1 << 0 + } fuseable_ops: 1; /* Depth of scheduling queue to check for L2 autoprefetcher. */ - enum arm_sched_autopref sched_autopref; - /* Issue rate of the processor. */ - unsigned int issue_rate; + enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL} + sched_autopref: 2; }; +/* Smash multiple fusion operations into a type that can be used for an + initializer. */ +#define FUSE_OPS(x) ((tune_params::fuse_ops) (x)) + extern const struct tune_params *current_tune; extern int vfp3_const_double_for_fract_bits (rtx); /* return power of two from operand, otherwise 0. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index cf4f248..3123af3 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -935,11 +935,13 @@ struct processors }; -#define ARM_PREFETCH_NOT_BENEFICIAL 0, -1, -1 -#define ARM_PREFETCH_BENEFICIAL(prefetch_slots,l1_size,l1_line_size) \ - prefetch_slots, \ - l1_size, \ - l1_line_size +#define ARM_PREFETCH_NOT_BENEFICIAL { 0, -1, -1 } +#define ARM_PREFETCH_BENEFICIAL(num_slots,l1_size,l1_line_size) \ + { \ + num_slots, \ + l1_size, \ + l1_line_size \ + } /* arm generic vectorizer costs. */ static const @@ -1673,51 +1675,50 @@ const struct cpu_cost_table v7m_extra_costs = } }; -#define ARM_FUSE_NOTHING (0) -#define ARM_FUSE_MOVW_MOVT (1 << 0) - const struct tune_params arm_slowmul_tune = { arm_slowmul_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 3, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_fastmul_tune = { arm_fastmul_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; /* StrongARM has early execution of branches, so a sequence that is worth @@ -1726,111 +1727,116 @@ const struct tune_params arm_fastmul_tune = const struct tune_params arm_strongarm_tune = { arm_fastmul_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 3, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_xscale_tune = { arm_xscale_rtx_costs, - NULL, + NULL, /* Insn extra costs. */ xscale_sched_adjust_cost, + arm_default_branch_cost, + &arm_default_vec_cost, 2, /* Constant limit. */ 3, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_9e_tune = { arm_9e_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_marvell_pj4_tune = { arm_9e_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_v6t2_tune = { arm_9e_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; @@ -1839,154 +1845,161 @@ const struct tune_params arm_cortex_tune = { arm_9e_rtx_costs, &generic_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_cortex_a8_tune = { arm_9e_rtx_costs, &cortexa8_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_cortex_a7_tune = { arm_9e_rtx_costs, &cortexa7_extra_costs, - NULL, + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_cortex_a15_tune = { arm_9e_rtx_costs, &cortexa15_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 3, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - true, true, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_FULL, /* Sched L2 autopref. */ - 3 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_FULL }; const struct tune_params arm_cortex_a53_tune = { arm_9e_rtx_costs, &cortexa53_extra_costs, - NULL, /* Scheduler cost adjustment. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_MOVW_MOVT, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + FUSE_OPS (tune_params::FUSE_MOVW_MOVT), + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_cortex_a57_tune = { arm_9e_rtx_costs, &cortexa57_extra_costs, - NULL, /* Scheduler cost adjustment. */ - 1, /* Constant limit. */ - 2, /* Max cond insns. */ - ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ + NULL, /* Sched adj cost. */ arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - true, true, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_MOVW_MOVT, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_FULL, /* Sched L2 autopref. */ - 3 /* Issue rate. */ + &arm_default_vec_cost, + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 3, /* Issue rate. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + FUSE_OPS (tune_params::FUSE_MOVW_MOVT), + tune_params::SCHED_AUTOPREF_FULL }; const struct tune_params arm_xgene1_tune = { arm_9e_rtx_costs, &xgene1_extra_costs, - NULL, /* Scheduler cost adjustment. */ - 1, /* Constant limit. */ - 2, /* Max cond insns. */ - ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ + NULL, /* Sched adj cost. */ arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - true, true, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 32, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 4 /* Issue rate. */ + &arm_default_vec_cost, + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + 32, /* Memset max inline. */ + 4, /* Issue rate. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is @@ -1996,22 +2009,23 @@ const struct tune_params arm_cortex_a5_tune = { arm_9e_rtx_costs, &cortexa5_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_cortex_a5_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 1, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_cortex_a5_branch_cost, - false, /* Prefer LDRD/STRD. */ - {false, false}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_FALSE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_FALSE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_cortex_a9_tune = @@ -2019,43 +2033,45 @@ const struct tune_params arm_cortex_a9_tune = arm_9e_rtx_costs, &cortexa9_extra_costs, cortex_a9_sched_adjust_cost, + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_BENEFICIAL(4,32,32), - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_cortex_a12_tune = { arm_9e_rtx_costs, &cortexa12_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - true, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - true, true, /* Prefer 32-bit encodings. */ - true, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_MOVW_MOVT, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_TRUE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_ALL, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_TRUE, + FUSE_OPS (tune_params::FUSE_MOVW_MOVT), + tune_params::SCHED_AUTOPREF_OFF }; /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single @@ -2069,22 +2085,23 @@ const struct tune_params arm_v7m_tune = { arm_9e_rtx_costs, &v7m_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_cortex_m_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_cortex_m_branch_cost, - false, /* Prefer LDRD/STRD. */ - {false, false}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_FALSE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_FALSE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; /* Cortex-M7 tuning. */ @@ -2093,22 +2110,23 @@ const struct tune_params arm_cortex_m7_tune = { arm_9e_rtx_costs, &v7m_extra_costs, - NULL, /* Sched adj cost. */ + NULL, /* Sched adj cost. */ + arm_cortex_m7_branch_cost, + &arm_default_vec_cost, 0, /* Constant limit. */ 1, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_cortex_m7_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than @@ -2116,45 +2134,47 @@ const struct tune_params arm_cortex_m7_tune = const struct tune_params arm_v6m_tune = { arm_9e_rtx_costs, - NULL, - NULL, /* Sched adj cost. */ + NULL, /* Insn extra costs. */ + NULL, /* Sched adj cost. */ + arm_default_branch_cost, + &arm_default_vec_cost, /* Vectorizer costs. */ 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - false, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {false, false}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 1 /* Issue rate. */ + tune_params::PREF_CONST_POOL_FALSE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_FALSE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_FALSE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; const struct tune_params arm_fa726te_tune = { arm_9e_rtx_costs, - NULL, + NULL, /* Insn extra costs. */ fa726te_sched_adjust_cost, + arm_default_branch_cost, + &arm_default_vec_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ + 8, /* Memset max inline. */ + 2, /* Issue rate. */ ARM_PREFETCH_NOT_BENEFICIAL, - true, /* Prefer constant pool. */ - arm_default_branch_cost, - false, /* Prefer LDRD/STRD. */ - {true, true}, /* Prefer non short circuit. */ - &arm_default_vec_cost, /* Vectorizer costs. */ - false, /* Prefer Neon for 64-bits bitops. */ - false, false, /* Prefer 32-bit encodings. */ - false, /* Prefer Neon for stringops. */ - 8, /* Maximum insns to inline memset. */ - ARM_FUSE_NOTHING, /* Fuseable pairs of instructions. */ - ARM_SCHED_AUTOPREF_OFF, /* Sched L2 autopref. */ - 2 /* Issue rate. */ + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SC_TRUE, /* Thumb. */ + tune_params::LOG_OP_NON_SC_TRUE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_64_FALSE, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF }; @@ -3228,31 +3248,33 @@ arm_option_override (void) && abi_version_at_least(2)) flag_strict_volatile_bitfields = 1; - /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed - it beneficial (signified by setting num_prefetch_slots to 1 or more.) */ + /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we + have deemed it beneficial (signified by setting + prefetch.num_slots to 1 or more). */ if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3 - && current_tune->num_prefetch_slots > 0) + && current_tune->prefetch.num_slots > 0) flag_prefetch_loop_arrays = 1; - /* Set up parameters to be used in prefetching algorithm. Do not override the - defaults unless we are tuning for a core we have researched values for. */ - if (current_tune->num_prefetch_slots > 0) + /* Set up parameters to be used in prefetching algorithm. Do not + override the defaults unless we are tuning for a core we have + researched values for. */ + if (current_tune->prefetch.num_slots > 0) maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, - current_tune->num_prefetch_slots, - global_options.x_param_values, - global_options_set.x_param_values); - if (current_tune->l1_cache_line_size >= 0) + current_tune->prefetch.num_slots, + global_options.x_param_values, + global_options_set.x_param_values); + if (current_tune->prefetch.l1_cache_line_size >= 0) maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, - current_tune->l1_cache_line_size, - global_options.x_param_values, - global_options_set.x_param_values); - if (current_tune->l1_cache_size >= 0) + current_tune->prefetch.l1_cache_line_size, + global_options.x_param_values, + global_options_set.x_param_values); + if (current_tune->prefetch.l1_cache_size >= 0) maybe_set_param_value (PARAM_L1_CACHE_SIZE, - current_tune->l1_cache_size, - global_options.x_param_values, - global_options_set.x_param_values); + current_tune->prefetch.l1_cache_size, + global_options.x_param_values, + global_options_set.x_param_values); /* Use Neon to perform 64-bits operations rather than core registers. */ @@ -3262,24 +3284,35 @@ arm_option_override (void) /* Use the alternative scheduling-pressure algorithm by default. */ maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PRESSURE_MODEL, - global_options.x_param_values, - global_options_set.x_param_values); + global_options.x_param_values, + global_options_set.x_param_values); /* Look through ready list and all of queue for instructions relevant for L2 auto-prefetcher. */ int param_sched_autopref_queue_depth; - if (current_tune->sched_autopref == ARM_SCHED_AUTOPREF_OFF) - param_sched_autopref_queue_depth = -1; - else if (current_tune->sched_autopref == ARM_SCHED_AUTOPREF_RANK) - param_sched_autopref_queue_depth = 0; - else if (current_tune->sched_autopref == ARM_SCHED_AUTOPREF_FULL) - param_sched_autopref_queue_depth = max_insn_queue_index + 1; - else - gcc_unreachable (); + + switch (current_tune->sched_autopref) + { + case tune_params::SCHED_AUTOPREF_OFF: + param_sched_autopref_queue_depth = -1; + break; + + case tune_params::SCHED_AUTOPREF_RANK: + param_sched_autopref_queue_depth = 0; + break; + + case tune_params::SCHED_AUTOPREF_FULL: + param_sched_autopref_queue_depth = max_insn_queue_index + 1; + break; + + default: + gcc_unreachable (); + } + maybe_set_param_value (PARAM_SCHED_AUTOPREF_QUEUE_DEPTH, param_sched_autopref_queue_depth, - global_options.x_param_values, - global_options_set.x_param_values); + global_options.x_param_values, + global_options_set.x_param_values); /* Currently, for slow flash data, we just disable literal pools. */ if (target_slow_flash_data) @@ -17084,14 +17117,16 @@ thumb2_reorg (void) FOR_EACH_BB_FN (bb, cfun) { - if (current_tune->disparage_flag_setting_t16_encodings + if ((current_tune->disparage_flag_setting_t16_encodings + == tune_params::DISPARAGE_FLAGS_ALL) && optimize_bb_for_speed_p (bb)) continue; rtx_insn *insn; Convert_Action action = SKIP; Convert_Action action_for_partial_flag_setting - = (current_tune->disparage_partial_flag_setting_t16_encodings + = ((current_tune->disparage_flag_setting_t16_encodings + != tune_params::DISPARAGE_FLAGS_NEITHER) && optimize_bb_for_speed_p (bb)) ? SKIP : CONV; @@ -25434,12 +25469,12 @@ arm_print_tune_info (void) current_tune->constant_limit); asm_fprintf (asm_out_file, "\t\t@max_insns_skipped:\t%d\n", current_tune->max_insns_skipped); - asm_fprintf (asm_out_file, "\t\t@num_prefetch_slots:\t%d\n", - current_tune->num_prefetch_slots); - asm_fprintf (asm_out_file, "\t\t@l1_cache_size:\t%d\n", - current_tune->l1_cache_size); - asm_fprintf (asm_out_file, "\t\t@l1_cache_line_size:\t%d\n", - current_tune->l1_cache_line_size); + asm_fprintf (asm_out_file, "\t\t@prefetch.num_slots:\t%d\n", + current_tune->prefetch.num_slots); + asm_fprintf (asm_out_file, "\t\t@prefetch.l1_cache_size:\t%d\n", + current_tune->prefetch.l1_cache_size); + asm_fprintf (asm_out_file, "\t\t@prefetch.l1_cache_line_size:\t%d\n", + current_tune->prefetch.l1_cache_line_size); asm_fprintf (asm_out_file, "\t\t@prefer_constant_pool:\t%d\n", (int) current_tune->prefer_constant_pool); asm_fprintf (asm_out_file, "\t\t@branch_cost:\t(s:speed, p:predictable)\n"); @@ -25455,17 +25490,13 @@ arm_print_tune_info (void) asm_fprintf (asm_out_file, "\t\t@prefer_ldrd_strd:\t%d\n", (int) current_tune->prefer_ldrd_strd); asm_fprintf (asm_out_file, "\t\t@logical_op_non_short_circuit:\t[%d,%d]\n", - (int) current_tune->logical_op_non_short_circuit[0], - (int) current_tune->logical_op_non_short_circuit[1]); + (int) current_tune->logical_op_non_short_circuit_thumb, + (int) current_tune->logical_op_non_short_circuit_arm); asm_fprintf (asm_out_file, "\t\t@prefer_neon_for_64bits:\t%d\n", (int) current_tune->prefer_neon_for_64bits); asm_fprintf (asm_out_file, "\t\t@disparage_flag_setting_t16_encodings:\t%d\n", (int) current_tune->disparage_flag_setting_t16_encodings); - asm_fprintf (asm_out_file, - "\t\t@disparage_partial_flag_setting_t16_encodings:\t%d\n", - (int) current_tune - ->disparage_partial_flag_setting_t16_encodings); asm_fprintf (asm_out_file, "\t\t@string_ops_prefer_neon:\t%d\n", (int) current_tune->string_ops_prefer_neon); asm_fprintf (asm_out_file, "\t\t@max_insns_inline_memset:\t%d\n", @@ -29112,7 +29143,7 @@ arm_gen_setmem (rtx *operands) static bool arm_macro_fusion_p (void) { - return current_tune->fuseable_ops != ARM_FUSE_NOTHING; + return current_tune->fuseable_ops != tune_params::FUSE_NOTHING; } @@ -29133,44 +29164,44 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr) if (!arm_macro_fusion_p ()) return false; - if (current_tune->fuseable_ops & ARM_FUSE_MOVW_MOVT) + if (current_tune->fuseable_ops & tune_params::FUSE_MOVW_MOVT) { /* We are trying to fuse - movw imm / movt imm - instructions as a group that gets scheduled together. */ + movw imm / movt imm + instructions as a group that gets scheduled together. */ set_dest = SET_DEST (curr_set); if (GET_MODE (set_dest) != SImode) - return false; + return false; /* We are trying to match: - prev (movw) == (set (reg r0) (const_int imm16)) - curr (movt) == (set (zero_extract (reg r0) - (const_int 16) - (const_int 16)) - (const_int imm16_1)) - or - prev (movw) == (set (reg r1) - (high (symbol_ref ("SYM")))) - curr (movt) == (set (reg r0) - (lo_sum (reg r1) - (symbol_ref ("SYM")))) */ + prev (movw) == (set (reg r0) (const_int imm16)) + curr (movt) == (set (zero_extract (reg r0) + (const_int 16) + (const_int 16)) + (const_int imm16_1)) + or + prev (movw) == (set (reg r1) + (high (symbol_ref ("SYM")))) + curr (movt) == (set (reg r0) + (lo_sum (reg r1) + (symbol_ref ("SYM")))) */ if (GET_CODE (set_dest) == ZERO_EXTRACT) - { - if (CONST_INT_P (SET_SRC (curr_set)) - && CONST_INT_P (SET_SRC (prev_set)) - && REG_P (XEXP (set_dest, 0)) - && REG_P (SET_DEST (prev_set)) - && REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set))) - return true; - } + { + if (CONST_INT_P (SET_SRC (curr_set)) + && CONST_INT_P (SET_SRC (prev_set)) + && REG_P (XEXP (set_dest, 0)) + && REG_P (SET_DEST (prev_set)) + && REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set))) + return true; + } else if (GET_CODE (SET_SRC (curr_set)) == LO_SUM - && REG_P (SET_DEST (curr_set)) - && REG_P (SET_DEST (prev_set)) - && GET_CODE (SET_SRC (prev_set)) == HIGH - && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set))) - return true; + && REG_P (SET_DEST (curr_set)) + && REG_P (SET_DEST (prev_set)) + && GET_CODE (SET_SRC (prev_set)) == HIGH + && REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set))) + return true; } return false; } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ba37c42..8574388 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2057,10 +2057,11 @@ enum arm_auto_incmodes (current_tune->branch_cost (speed_p, predictable_p)) /* False if short circuit operation is preferred. */ -#define LOGICAL_OP_NON_SHORT_CIRCUIT \ - ((optimize_size) \ - ? (TARGET_THUMB ? false : true) \ - : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) +#define LOGICAL_OP_NON_SHORT_CIRCUIT \ + ((optimize_size) \ + ? (TARGET_THUMB ? false : true) \ + : TARGET_THUMB ? current_tune->logical_op_non_short_circuit_thumb \ + : current_tune->logical_op_non_short_circuit_arm) /* Position Independent Code. */