| Message ID | 54639F40.5030309@arm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Nov 12, 2014 at 6:56 PM, Alan Lawrence <alan.lawrence@arm.com> wrote: > This redefines vec_shr optab to be the same (in terms of gcc vectors) > regardless of target endianness. The vectorizer uses this to do reductions > via shifts, so also change the vectorizer to shift things always the same > way (from the midend's POV of vectors). > > cross-tested check-gcc on (1) aarch64-none-elf and (2) aarch64_be-none-elf, > both (a) using the endianness-independent vec_shr patterns at > https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01477.html and (b) in present > state without any vec_shr patterns. No regressions on any combination. > > Bootstrap + check-gcc on x86_64-none-linux-gnu. > > This patch will break MIPS and PowerPC (which have bigendian vec_shr > patterns). Candidate MIPS fix previously posted at > https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01481.html . > PowerPC should be fixed by > https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01480.html ; I've bootstrapped > this on powerpc64-unknown-linux-gnu, check-gcc in progress. Ok. Thanks. Richard. > gcc/ChangeLog: > > * optabs.c (shift_amt_for_vec_perm_mask): Remove code conditional on > BYTES_BIG_ENDIAN. > * tree-vect-loop.c (calc_vec_perm_mask_for_shift, > vect_create_epilog_for_reduction): Likewise. > * doc/md.texi (vec_shr_m): Clarify direction of shifting.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 3b5511ec39a86fb4278ebd766420eaec5eb05d8b..3742ca3e3f1c428ae8a84885969b31806df02ebd 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4798,7 +4798,7 @@ of a wider mode.) @cindex @code{vec_shr_@var{m}} instruction pattern @item @samp{vec_shr_@var{m}} -Whole vector right shift in bits. +Whole vector right shift in bits, i.e. towards element 0. Operand 1 is a vector to be shifted. Operand 2 is an integer shift amount in bits. Operand 0 is where the resulting shifted vector is stored. diff --git a/gcc/optabs.c b/gcc/optabs.c index 9650b58a8ed2c6701f653c0d6c15dba71b04b089..6e8f52e1d88844b060857356ac2ec8b7cba059c6 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -6626,8 +6626,6 @@ shift_amt_for_vec_perm_mask (rtx sel) return NULL_RTX; } - if (BYTES_BIG_ENDIAN) - first = (2 * nelt) - first; return GEN_INT (first * bitsize); } diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index f1d327f42a5c517a01121135569dd014e49502e0..91d82b72d0f0ef944d0fa5c23da36aff0384a9d0 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -3091,7 +3091,7 @@ calc_vec_perm_mask_for_shift (enum machine_mode mode, unsigned int offset, unsigned int i, nelt = GET_MODE_NUNITS (mode); for (i = 0; i < nelt; i++) - sel[i] = (BYTES_BIG_ENDIAN ? i - offset : i + offset) & (2*nelt - 1); + sel[i] = (i + offset) & (2*nelt - 1); } /* Checks whether the target supports whole-vector shifts for vectors of mode @@ -3906,7 +3906,7 @@ vect_create_epilog_for_reduction (vec<tree> vect_defs, gimple stmt, gimple epilog_stmt = NULL; enum tree_code code = gimple_assign_rhs_code (stmt); gimple exit_phi; - tree bitsize, bitpos; + tree bitsize; tree adjustment_def = NULL; tree vec_initial_def = NULL; tree reduction_op, expr, def; @@ -4416,14 +4416,8 @@ vect_create_epilog_for_reduction (vec<tree> vect_defs, gimple stmt, dump_printf_loc (MSG_NOTE, vect_location, "extract scalar result\n"); - if (BYTES_BIG_ENDIAN) - bitpos = size_binop (MULT_EXPR, - bitsize_int (TYPE_VECTOR_SUBPARTS (vectype) - 1), - TYPE_SIZE (scalar_type)); - else - bitpos = bitsize_zero_node; - - rhs = build3 (BIT_FIELD_REF, scalar_type, new_temp, bitsize, bitpos); + rhs = build3 (BIT_FIELD_REF, scalar_type, + new_temp, bitsize, bitsize_zero_node); epilog_stmt = gimple_build_assign (new_scalar_dest, rhs); new_temp = make_ssa_name (new_scalar_dest, epilog_stmt); gimple_assign_set_lhs (epilog_stmt, new_temp);