[AArch64,RTL] Bics instruction generation for aarch64

From 98bb6d7323ce79e28be8ef892b919391ed857e1f Mon Sep 17 00:00:00 2001
From: Alex Velenko <alex.velenko@arm.com>
Date: Fri, 31 Oct 2014 18:43:32 +0000
Subject: [PATCH] [AArch64, RTL] Bics instruction generation for aarch64

Hi,

This patch adds rtl patterns for aarch64 to generate bics instructions in
cases when caputed value gets discarded and only only the status regester
change of the instruction gets reused.

Previously, bics would only be generated, if the value computed by bics
would later be reused, which is not necessarily the case when computing
this value for "if" statements.

Is this patch ok?

Thanks,
Alex

gcc/

2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>

     * gcc/config/aarch64/aarch64.md 
(and_one_cmpl<mode>3_compare0_no_reuse):
       New define_insn.
     * (and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse):
       Likewise.

gcc/testsuite/

2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>

     * gcc.target/aarch64/bics1.c : New testcase.
---
  gcc/config/aarch64/aarch64.md             | 26 ++++++++++++
  gcc/testsuite/gcc.target/aarch64/bics_3.c | 69 
+++++++++++++++++++++++++++++++
  2 files changed, 95 insertions(+)
  create mode 100644 gcc/testsuite/gcc.target/aarch64/bics_3.c

+/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+, 
lsl 2" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */

On 11/11/14 10:38, Alex Velenko wrote:
>  From 98bb6d7323ce79e28be8ef892b919391ed857e1f Mon Sep 17 00:00:00 2001
> From: Alex Velenko <alex.velenko@arm.com>
> Date: Fri, 31 Oct 2014 18:43:32 +0000
> Subject: [PATCH] [AArch64, RTL] Bics instruction generation for aarch64
>
> Hi,
>
> This patch adds rtl patterns for aarch64 to generate bics instructions in
> cases when caputed value gets discarded and only only the status regester
> change of the instruction gets reused.
>
> Previously, bics would only be generated, if the value computed by bics
> would later be reused, which is not necessarily the case when computing
> this value for "if" statements.
>
> Is this patch ok?
>
> Thanks,
> Alex
>
> gcc/
>
> 2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>
>
>      * gcc/config/aarch64/aarch64.md
> (and_one_cmpl<mode>3_compare0_no_reuse):
>        New define_insn.
>      * (and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse):
>        Likewise.
>
> gcc/testsuite/
>
> 2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>
>
>      * gcc.target/aarch64/bics1.c : New testcase.
> ---
>   gcc/config/aarch64/aarch64.md             | 26 ++++++++++++
>   gcc/testsuite/gcc.target/aarch64/bics_3.c | 69
> +++++++++++++++++++++++++++++++
>   2 files changed, 95 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/bics_3.c
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 341c26f..6158d82 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2845,6 +2845,18 @@
>     [(set_attr "type" "logics_reg")]
>   )
>
> +(define_insn "*and_one_cmpl<mode>3_compare0_no_reuse"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +    (compare:CC_NZ
> +     (and:GPI (not:GPI
> +           (match_operand:GPI 0 "register_operand" "r"))
> +          (match_operand:GPI 1 "register_operand" "r"))
> +     (const_int 0)))]
> +  ""
> +  "bics\\t<w>zr, %<w>1, %<w>0"
> +  [(set_attr "type" "logics_reg")]
> +)
> +
>   (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
>     [(set (match_operand:GPI 0 "register_operand" "=r")
>       (LOGICAL:GPI (not:GPI
> @@ -2894,6 +2906,20 @@
>     [(set_attr "type" "logics_shift_imm")]
>   )
>
> +(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +    (compare:CC_NZ
> +     (and:GPI (not:GPI
> +           (SHIFT:GPI
> +            (match_operand:GPI 0 "register_operand" "r")
> +            (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n")))
> +          (match_operand:GPI 2 "register_operand" "r"))
> +     (const_int 0)))]
> +  ""
> +  "bics\\t<w>zr, %<w>2, %<w>0, <SHIFT:shift> %1"
> +  [(set_attr "type" "logics_shift_imm")]
> +)
> +
>   (define_insn "clz<mode>2"
>     [(set (match_operand:GPI 0 "register_operand" "=r")
>       (clz:GPI (match_operand:GPI 1 "register_operand" "r")))]
> diff --git a/gcc/testsuite/gcc.target/aarch64/bics_3.c
> b/gcc/testsuite/gcc.target/aarch64/bics_3.c
> new file mode 100644
> index 0000000..ecb53e9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/bics_3.c
> @@ -0,0 +1,69 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 --save-temps" } */
> +
> +extern void abort (void);
> +
> +int __attribute__ ((noinline))
> +bics_si_test (int a, int b)
> +{
> +  if (a & ~b)
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +int __attribute__ ((noinline))
> +bics_si_test2 (int a, int b)
> +{
> +  if (a & ~ (b << 2))
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +typedef long long s64;
> +
> +int __attribute__ ((noinline))
> +bics_di_test (s64 a, s64 b)
> +{
> +  if (a & ~b)
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +int __attribute__ ((noinline))
> +bics_di_test2 (s64 a, s64 b)
> +{
> +  if (a & ~(b << 2))
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +int
> +main (void)
> +{
> +  int a = 5;
> +  int b = 5;
> +  int c = 20;
> +  s64 d = 5;
> +  s64 e = 5;
> +  s64 f = 20;
> +  if (bics_si_test (a, b))
> +    abort ();
> +  if (bics_si_test2 (c, b))
> +    abort ();
> +  if (bics_di_test (d, e))
> +    abort ();
> +  if (bics_di_test2 (f, e))
> +    abort ();
> +  return 0;
> +}
> +
> +/* { dg-final { scan-assembler-times "bics\twzr, w\[0-9\]+, w\[0-9\]+"
> 2 } } */
> +/* { dg-final { scan-assembler-times "bics\twzr, w\[0-9\]+, w\[0-9\]+,
> lsl 2" 1 } } */
> +/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+"
> 2 } } */
> +/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+,
> lsl 2" 1 } } */
> +
> +/* { dg-final { cleanup-saved-temps } } */

Hi,
Could someone, please, approve?
Kind regards,
Alex

On 11/11/14 10:38, Alex Velenko wrote:
>  From 98bb6d7323ce79e28be8ef892b919391ed857e1f Mon Sep 17 00:00:00 2001
> From: Alex Velenko <alex.velenko@arm.com>
> Date: Fri, 31 Oct 2014 18:43:32 +0000
> Subject: [PATCH] [AArch64, RTL] Bics instruction generation for aarch64
> 
> Hi,
> 
> This patch adds rtl patterns for aarch64 to generate bics instructions in
> cases when caputed value gets discarded and only only the status regester
> change of the instruction gets reused.
> 
> Previously, bics would only be generated, if the value computed by bics
> would later be reused, which is not necessarily the case when computing
> this value for "if" statements.
> 
> Is this patch ok?
> 
> Thanks,
> Alex
> 
> gcc/
> 
> 2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>
> 
>      * gcc/config/aarch64/aarch64.md 
> (and_one_cmpl<mode>3_compare0_no_reuse):
>        New define_insn.
>      * (and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse):
>        Likewise.
> 
> gcc/testsuite/
> 
> 2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>
> 
>      * gcc.target/aarch64/bics1.c : New testcase.

OK.

R.

> ---
>   gcc/config/aarch64/aarch64.md             | 26 ++++++++++++
>   gcc/testsuite/gcc.target/aarch64/bics_3.c | 69 
> +++++++++++++++++++++++++++++++
>   2 files changed, 95 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/aarch64/bics_3.c
> 
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 341c26f..6158d82 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -2845,6 +2845,18 @@
>     [(set_attr "type" "logics_reg")]
>   )
> 
> +(define_insn "*and_one_cmpl<mode>3_compare0_no_reuse"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +    (compare:CC_NZ
> +     (and:GPI (not:GPI
> +           (match_operand:GPI 0 "register_operand" "r"))
> +          (match_operand:GPI 1 "register_operand" "r"))
> +     (const_int 0)))]
> +  ""
> +  "bics\\t<w>zr, %<w>1, %<w>0"
> +  [(set_attr "type" "logics_reg")]
> +)
> +
>   (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
>     [(set (match_operand:GPI 0 "register_operand" "=r")
>       (LOGICAL:GPI (not:GPI
> @@ -2894,6 +2906,20 @@
>     [(set_attr "type" "logics_shift_imm")]
>   )
> 
> +(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +    (compare:CC_NZ
> +     (and:GPI (not:GPI
> +           (SHIFT:GPI
> +            (match_operand:GPI 0 "register_operand" "r")
> +            (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n")))
> +          (match_operand:GPI 2 "register_operand" "r"))
> +     (const_int 0)))]
> +  ""
> +  "bics\\t<w>zr, %<w>2, %<w>0, <SHIFT:shift> %1"
> +  [(set_attr "type" "logics_shift_imm")]
> +)
> +
>   (define_insn "clz<mode>2"
>     [(set (match_operand:GPI 0 "register_operand" "=r")
>       (clz:GPI (match_operand:GPI 1 "register_operand" "r")))]
> diff --git a/gcc/testsuite/gcc.target/aarch64/bics_3.c 
> b/gcc/testsuite/gcc.target/aarch64/bics_3.c
> new file mode 100644
> index 0000000..ecb53e9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/bics_3.c
> @@ -0,0 +1,69 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 --save-temps" } */
> +
> +extern void abort (void);
> +
> +int __attribute__ ((noinline))
> +bics_si_test (int a, int b)
> +{
> +  if (a & ~b)
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +int __attribute__ ((noinline))
> +bics_si_test2 (int a, int b)
> +{
> +  if (a & ~ (b << 2))
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +typedef long long s64;
> +
> +int __attribute__ ((noinline))
> +bics_di_test (s64 a, s64 b)
> +{
> +  if (a & ~b)
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +int __attribute__ ((noinline))
> +bics_di_test2 (s64 a, s64 b)
> +{
> +  if (a & ~(b << 2))
> +    return 1;
> +  else
> +    return 0;
> +}
> +
> +int
> +main (void)
> +{
> +  int a = 5;
> +  int b = 5;
> +  int c = 20;
> +  s64 d = 5;
> +  s64 e = 5;
> +  s64 f = 20;
> +  if (bics_si_test (a, b))
> +    abort ();
> +  if (bics_si_test2 (c, b))
> +    abort ();
> +  if (bics_di_test (d, e))
> +    abort ();
> +  if (bics_di_test2 (f, e))
> +    abort ();
> +  return 0;
> +}
> +
> +/* { dg-final { scan-assembler-times "bics\twzr, w\[0-9\]+, w\[0-9\]+" 
> 2 } } */
> +/* { dg-final { scan-assembler-times "bics\twzr, w\[0-9\]+, w\[0-9\]+, 
> lsl 2" 1 } } */
> +/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+" 
> 2 } } */
> +/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+, 
> lsl 2" 1 } } */
> +
> +/* { dg-final { cleanup-saved-temps } } */
>

On 08/12/14 10:33, Richard Earnshaw wrote:
> On 11/11/14 10:38, Alex Velenko wrote:
>>   From 98bb6d7323ce79e28be8ef892b919391ed857e1f Mon Sep 17 00:00:00 2001
>> From: Alex Velenko <alex.velenko@arm.com>
>> Date: Fri, 31 Oct 2014 18:43:32 +0000
>> Subject: [PATCH] [AArch64, RTL] Bics instruction generation for aarch64
>>
>> Hi,
>>
>> This patch adds rtl patterns for aarch64 to generate bics instructions in
>> cases when caputed value gets discarded and only only the status regester
>> change of the instruction gets reused.
>>
>> Previously, bics would only be generated, if the value computed by bics
>> would later be reused, which is not necessarily the case when computing
>> this value for "if" statements.
>>
>> Is this patch ok?
>>
>> Thanks,
>> Alex
>>
>> gcc/
>>
>> 2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>
>>
>>       * gcc/config/aarch64/aarch64.md
>> (and_one_cmpl<mode>3_compare0_no_reuse):
>>         New define_insn.
>>       * (and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse):
>>         Likewise.
>>
>> gcc/testsuite/
>>
>> 2014-11-10  Alex Velenko  <Alex.Velenko@arm.com>
>>
>>       * gcc.target/aarch64/bics1.c : New testcase.
>
> OK.
>
> R.
>
Committed,

Alex

>> ---
>>    gcc/config/aarch64/aarch64.md             | 26 ++++++++++++
>>    gcc/testsuite/gcc.target/aarch64/bics_3.c | 69
>> +++++++++++++++++++++++++++++++
>>    2 files changed, 95 insertions(+)
>>    create mode 100644 gcc/testsuite/gcc.target/aarch64/bics_3.c
>>
>> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
>> index 341c26f..6158d82 100644
>> --- a/gcc/config/aarch64/aarch64.md
>> +++ b/gcc/config/aarch64/aarch64.md
>> @@ -2845,6 +2845,18 @@
>>      [(set_attr "type" "logics_reg")]
>>    )
>>
>> +(define_insn "*and_one_cmpl<mode>3_compare0_no_reuse"
>> +  [(set (reg:CC_NZ CC_REGNUM)
>> +    (compare:CC_NZ
>> +     (and:GPI (not:GPI
>> +           (match_operand:GPI 0 "register_operand" "r"))
>> +          (match_operand:GPI 1 "register_operand" "r"))
>> +     (const_int 0)))]
>> +  ""
>> +  "bics\\t<w>zr, %<w>1, %<w>0"
>> +  [(set_attr "type" "logics_reg")]
>> +)
>> +
>>    (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
>>      [(set (match_operand:GPI 0 "register_operand" "=r")
>>        (LOGICAL:GPI (not:GPI
>> @@ -2894,6 +2906,20 @@
>>      [(set_attr "type" "logics_shift_imm")]
>>    )
>>
>> +(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse"
>> +  [(set (reg:CC_NZ CC_REGNUM)
>> +    (compare:CC_NZ
>> +     (and:GPI (not:GPI
>> +           (SHIFT:GPI
>> +            (match_operand:GPI 0 "register_operand" "r")
>> +            (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n")))
>> +          (match_operand:GPI 2 "register_operand" "r"))
>> +     (const_int 0)))]
>> +  ""
>> +  "bics\\t<w>zr, %<w>2, %<w>0, <SHIFT:shift> %1"
>> +  [(set_attr "type" "logics_shift_imm")]
>> +)
>> +
>>    (define_insn "clz<mode>2"
>>      [(set (match_operand:GPI 0 "register_operand" "=r")
>>        (clz:GPI (match_operand:GPI 1 "register_operand" "r")))]
>> diff --git a/gcc/testsuite/gcc.target/aarch64/bics_3.c
>> b/gcc/testsuite/gcc.target/aarch64/bics_3.c
>> new file mode 100644
>> index 0000000..ecb53e9
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/bics_3.c
>> @@ -0,0 +1,69 @@
>> +/* { dg-do run } */
>> +/* { dg-options "-O2 --save-temps" } */
>> +
>> +extern void abort (void);
>> +
>> +int __attribute__ ((noinline))
>> +bics_si_test (int a, int b)
>> +{
>> +  if (a & ~b)
>> +    return 1;
>> +  else
>> +    return 0;
>> +}
>> +
>> +int __attribute__ ((noinline))
>> +bics_si_test2 (int a, int b)
>> +{
>> +  if (a & ~ (b << 2))
>> +    return 1;
>> +  else
>> +    return 0;
>> +}
>> +
>> +typedef long long s64;
>> +
>> +int __attribute__ ((noinline))
>> +bics_di_test (s64 a, s64 b)
>> +{
>> +  if (a & ~b)
>> +    return 1;
>> +  else
>> +    return 0;
>> +}
>> +
>> +int __attribute__ ((noinline))
>> +bics_di_test2 (s64 a, s64 b)
>> +{
>> +  if (a & ~(b << 2))
>> +    return 1;
>> +  else
>> +    return 0;
>> +}
>> +
>> +int
>> +main (void)
>> +{
>> +  int a = 5;
>> +  int b = 5;
>> +  int c = 20;
>> +  s64 d = 5;
>> +  s64 e = 5;
>> +  s64 f = 20;
>> +  if (bics_si_test (a, b))
>> +    abort ();
>> +  if (bics_si_test2 (c, b))
>> +    abort ();
>> +  if (bics_di_test (d, e))
>> +    abort ();
>> +  if (bics_di_test2 (f, e))
>> +    abort ();
>> +  return 0;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times "bics\twzr, w\[0-9\]+, w\[0-9\]+"
>> 2 } } */
>> +/* { dg-final { scan-assembler-times "bics\twzr, w\[0-9\]+, w\[0-9\]+,
>> lsl 2" 1 } } */
>> +/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+"
>> 2 } } */
>> +/* { dg-final { scan-assembler-times "bics\txzr, x\[0-9\]+, x\[0-9\]+,
>> lsl 2" 1 } } */
>> +
>> +/* { dg-final { cleanup-saved-temps } } */
>>
>