| Message ID | 541f060b-57b0-9632-081e-800804209b15@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [Arm] Enable MVE SIMD modes for vectorization | expand |
On 9/16/20 4:00 PM, Dennis Zhang wrote: > Hi all, > > This patch enables SIMD modes for MVE auto-vectorization. > In this patch, the integer and float MVE SIMD modes are returned by > arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > MVE or MVE_FLOAT is enabled. > Then the expanders for auto-vectorization can be used for generating MVE > SIMD code. > > This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > revealed by the enabled MVE SIMD modes. > The tests are for checking the MVE reinterpret intrinsics. > There are two functions in each of the tests. The two functions contain > the pattern of identical code so that they are folded in icf pass. > Because of icf, the instruction count only checks one function which is 8. > However when the SIMD modes are enabled, the estimation of the code size > becomes smaller so that inlining is applied after icf, then the > instruction count becomes 16 which causes failure of the tests. > Because the icf is not the expected pattern to be tested but causes > above issues, -fno-ipa-icf is applied to the tests to avoid unstable > instruction count. > > This patch is separated from > https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > because this part is not strongly connected to the aim of that one so > that causing confusion. > > Regtested and bootstraped. > > Is it OK for trunk please? > > Thanks > Dennis > > gcc/ChangeLog: > > 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. > > gcc/testsuite/ChangeLog: > > 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional > option -fno-ipa-icf and change the instruction count from 8 to 16. > * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. > * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. > Ping: https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554100.html
Hi Dennis, > -----Original Message----- > From: Dennis Zhang <Dennis.Zhang@arm.com> > Sent: 06 October 2020 14:37 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; nd <nd@arm.com>; > Richard Earnshaw <Richard.Earnshaw@arm.com>; Ramana Radhakrishnan > <Ramana.Radhakrishnan@arm.com> > Subject: Ping: [PATCH][Arm] Enable MVE SIMD modes for vectorization > > On 9/16/20 4:00 PM, Dennis Zhang wrote: > > Hi all, > > > > This patch enables SIMD modes for MVE auto-vectorization. > > In this patch, the integer and float MVE SIMD modes are returned by > > arm_preferred_simd_mode > (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > > MVE or MVE_FLOAT is enabled. > > Then the expanders for auto-vectorization can be used for generating MVE > > SIMD code. > > > > This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > > revealed by the enabled MVE SIMD modes. > > The tests are for checking the MVE reinterpret intrinsics. > > There are two functions in each of the tests. The two functions contain > > the pattern of identical code so that they are folded in icf pass. > > Because of icf, the instruction count only checks one function which is 8. > > However when the SIMD modes are enabled, the estimation of the code > size > > becomes smaller so that inlining is applied after icf, then the > > instruction count becomes 16 which causes failure of the tests. > > Because the icf is not the expected pattern to be tested but causes > > above issues, -fno-ipa-icf is applied to the tests to avoid unstable > > instruction count. > > > > This patch is separated from > > https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > > because this part is not strongly connected to the aim of that one so > > that causing confusion. > > > > Regtested and bootstraped. > > > > Is it OK for trunk please? Ok. Sorry for the delay. Kyrill > > > > Thanks > > Dennis > > > > gcc/ChangeLog: > > > > 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > > > * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD > modes. > > > > gcc/testsuite/ChangeLog: > > > > 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional > > option -fno-ipa-icf and change the instruction count from 8 to 16. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. > > > > Ping: https://gcc.gnu.org/pipermail/gcc-patches/2020- > September/554100.html
Hi, On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > On 9/16/20 4:00 PM, Dennis Zhang wrote: > > Hi all, > > > > This patch enables SIMD modes for MVE auto-vectorization. > > In this patch, the integer and float MVE SIMD modes are returned by > > arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > > MVE or MVE_FLOAT is enabled. > > Then the expanders for auto-vectorization can be used for generating MVE > > SIMD code. > > > > This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > > revealed by the enabled MVE SIMD modes. > > The tests are for checking the MVE reinterpret intrinsics. > > There are two functions in each of the tests. The two functions contain > > the pattern of identical code so that they are folded in icf pass. > > Because of icf, the instruction count only checks one function which is 8. > > However when the SIMD modes are enabled, the estimation of the code size > > becomes smaller so that inlining is applied after icf, then the > > instruction count becomes 16 which causes failure of the tests. > > Because the icf is not the expected pattern to be tested but causes > > above issues, -fno-ipa-icf is applied to the tests to avoid unstable > > instruction count. > > > > This patch is separated from > > https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > > because this part is not strongly connected to the aim of that one so > > that causing confusion. > > > > Regtested and bootstraped. > > > > Is it OK for trunk please? > > > > Thanks > > Dennis > > > > gcc/ChangeLog: > > > > 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > > > * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. > > Since toolchain builds work again after Jakub's divmod fix, I'm now facing another build error likely caused by this patch: In file included from /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/coretypes.h:449:0, from /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28: /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c: In function 'machine_mode arm_preferred_simd_mode(scalar_mode)': ./insn-modes.h:196:71: error: temporary of non-literal type 'scalar_int_mode' in a constant expression #define QImode (scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) ^ /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28970:12: note: in expansion of macro 'QImode' case QImode: and similarly for the other cases. Does the build work for you? Thanks, Christophe > > gcc/testsuite/ChangeLog: > > > > 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional > > option -fno-ipa-icf and change the instruction count from 8 to 16. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise. > > * gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise. > > > > Ping: https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554100.html
Hi Christophe, On 08/10/2020 14:14, Christophe Lyon wrote: > Hi, > > > On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches > <gcc-patches@gcc.gnu.org> wrote: >> >> On 9/16/20 4:00 PM, Dennis Zhang wrote: >>> Hi all, >>> >>> This patch enables SIMD modes for MVE auto-vectorization. >>> In this patch, the integer and float MVE SIMD modes are returned by >>> arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when >>> MVE or MVE_FLOAT is enabled. >>> Then the expanders for auto-vectorization can be used for generating MVE >>> SIMD code. >>> >>> This patch also fixes bugs in MVE vreiterpretq_*.c tests which are >>> revealed by the enabled MVE SIMD modes. >>> The tests are for checking the MVE reinterpret intrinsics. >>> There are two functions in each of the tests. The two functions contain >>> the pattern of identical code so that they are folded in icf pass. >>> Because of icf, the instruction count only checks one function which is 8. >>> However when the SIMD modes are enabled, the estimation of the code size >>> becomes smaller so that inlining is applied after icf, then the >>> instruction count becomes 16 which causes failure of the tests. >>> Because the icf is not the expected pattern to be tested but causes >>> above issues, -fno-ipa-icf is applied to the tests to avoid unstable >>> instruction count. >>> >>> This patch is separated from >>> https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html >>> because this part is not strongly connected to the aim of that one so >>> that causing confusion. >>> >>> Regtested and bootstraped. >>> >>> Is it OK for trunk please? >>> >>> Thanks >>> Dennis >>> >>> gcc/ChangeLog: >>> >>> 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> >>> >>> * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. >>> > > Since toolchain builds work again after Jakub's divmod fix, I'm now > facing another build error likely caused by this patch: > In file included from > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/coretypes.h:449:0, > from > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28: > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c: > In function 'machine_mode arm_preferred_simd_mode(scalar_mode)': > ./insn-modes.h:196:71: error: temporary of non-literal type > 'scalar_int_mode' in a constant expression > #define QImode (scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) > ^ > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28970:12: > note: in expansion of macro 'QImode' > case QImode: > > and similarly for the other cases. > > Does the build work for you? > > Thanks, > > Christophe > Thanks for the report. Sorry to see the error. I tested it for arm-none-eabi and arm-none-linux-gnueabi targets. I didn't get this error. Could you please help to show the configuration you use for your build? I will test and fix at once. Thanks Dennis
On Thu, 8 Oct 2020 at 16:08, Dennis Zhang <dennis.zhang@arm.com> wrote: > > Hi Christophe, > > On 08/10/2020 14:14, Christophe Lyon wrote: > > Hi, > > > > > > On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches > > <gcc-patches@gcc.gnu.org> wrote: > >> > >> On 9/16/20 4:00 PM, Dennis Zhang wrote: > >>> Hi all, > >>> > >>> This patch enables SIMD modes for MVE auto-vectorization. > >>> In this patch, the integer and float MVE SIMD modes are returned by > >>> arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > >>> MVE or MVE_FLOAT is enabled. > >>> Then the expanders for auto-vectorization can be used for generating MVE > >>> SIMD code. > >>> > >>> This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > >>> revealed by the enabled MVE SIMD modes. > >>> The tests are for checking the MVE reinterpret intrinsics. > >>> There are two functions in each of the tests. The two functions contain > >>> the pattern of identical code so that they are folded in icf pass. > >>> Because of icf, the instruction count only checks one function which is 8. > >>> However when the SIMD modes are enabled, the estimation of the code size > >>> becomes smaller so that inlining is applied after icf, then the > >>> instruction count becomes 16 which causes failure of the tests. > >>> Because the icf is not the expected pattern to be tested but causes > >>> above issues, -fno-ipa-icf is applied to the tests to avoid unstable > >>> instruction count. > >>> > >>> This patch is separated from > >>> https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > >>> because this part is not strongly connected to the aim of that one so > >>> that causing confusion. > >>> > >>> Regtested and bootstraped. > >>> > >>> Is it OK for trunk please? > >>> > >>> Thanks > >>> Dennis > >>> > >>> gcc/ChangeLog: > >>> > >>> 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > >>> > >>> * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. > >>> > > > > Since toolchain builds work again after Jakub's divmod fix, I'm now > > facing another build error likely caused by this patch: > > In file included from > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/coretypes.h:449:0, > > from > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28: > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c: > > In function 'machine_mode arm_preferred_simd_mode(scalar_mode)': > > ./insn-modes.h:196:71: error: temporary of non-literal type > > 'scalar_int_mode' in a constant expression > > #define QImode (scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) > > ^ > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28970:12: > > note: in expansion of macro 'QImode' > > case QImode: > > > > and similarly for the other cases. > > > > Does the build work for you? > > > > Thanks, > > > > Christophe > > > > Thanks for the report. Sorry to see the error. > I tested it for arm-none-eabi and arm-none-linux-gnueabi targets. I > didn't get this error. > Could you please help to show the configuration you use for your build? > I will test and fix at once. > It fails on all of them for me. Does it work for you with current master? (r11-3720-gf18eeb6b958acd5e1590ca4a73231486b749be9b) > Thanks > Dennis
Hi, On Thu, 8 Oct 2020 at 16:22, Christophe Lyon <christophe.lyon@linaro.org> wrote: > > On Thu, 8 Oct 2020 at 16:08, Dennis Zhang <dennis.zhang@arm.com> wrote: > > > > Hi Christophe, > > > > On 08/10/2020 14:14, Christophe Lyon wrote: > > > Hi, > > > > > > > > > On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches > > > <gcc-patches@gcc.gnu.org> wrote: > > >> > > >> On 9/16/20 4:00 PM, Dennis Zhang wrote: > > >>> Hi all, > > >>> > > >>> This patch enables SIMD modes for MVE auto-vectorization. > > >>> In this patch, the integer and float MVE SIMD modes are returned by > > >>> arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > > >>> MVE or MVE_FLOAT is enabled. > > >>> Then the expanders for auto-vectorization can be used for generating MVE > > >>> SIMD code. > > >>> > > >>> This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > > >>> revealed by the enabled MVE SIMD modes. > > >>> The tests are for checking the MVE reinterpret intrinsics. > > >>> There are two functions in each of the tests. The two functions contain > > >>> the pattern of identical code so that they are folded in icf pass. > > >>> Because of icf, the instruction count only checks one function which is 8. > > >>> However when the SIMD modes are enabled, the estimation of the code size > > >>> becomes smaller so that inlining is applied after icf, then the > > >>> instruction count becomes 16 which causes failure of the tests. > > >>> Because the icf is not the expected pattern to be tested but causes > > >>> above issues, -fno-ipa-icf is applied to the tests to avoid unstable > > >>> instruction count. > > >>> > > >>> This patch is separated from > > >>> https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html > > >>> because this part is not strongly connected to the aim of that one so > > >>> that causing confusion. > > >>> > > >>> Regtested and bootstraped. > > >>> > > >>> Is it OK for trunk please? > > >>> > > >>> Thanks > > >>> Dennis > > >>> > > >>> gcc/ChangeLog: > > >>> > > >>> 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > >>> > > >>> * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. > > >>> > > > > > > Since toolchain builds work again after Jakub's divmod fix, I'm now > > > facing another build error likely caused by this patch: > > > In file included from > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/coretypes.h:449:0, > > > from > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28: > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c: > > > In function 'machine_mode arm_preferred_simd_mode(scalar_mode)': > > > ./insn-modes.h:196:71: error: temporary of non-literal type > > > 'scalar_int_mode' in a constant expression > > > #define QImode (scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) > > > ^ > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28970:12: > > > note: in expansion of macro 'QImode' > > > case QImode: > > > > > > and similarly for the other cases. > > > > > > Does the build work for you? > > > > > > Thanks, > > > > > > Christophe > > > > > > > Thanks for the report. Sorry to see the error. > > I tested it for arm-none-eabi and arm-none-linux-gnueabi targets. I > > didn't get this error. > > Could you please help to show the configuration you use for your build? > > I will test and fix at once. > > > > It fails on all of them for me. Does it work for you with current > master? (r11-3720-gf18eeb6b958acd5e1590ca4a73231486b749be9b) > So... I guess you are using a host with GCC more recent than 4.8.5? :-) When I build manually on ubuntu-16.04 with gcc-5.4, the build succeeds, and after manually building with the same environment in the compute farm I use for validation (RHEL 7, gcc-4.8.5), I managed to reproduce the build failure. It's a matter of replacing case QImode: with case E_QImode: Is the attached patch OK? Or do we instead want to revisit the minimum gcc version required to build gcc? Thanks, Christophe > > Thanks > > Dennis gcc-4.8.5 does not accept case clauses with non-literal type, which happens for "QImode" as it expands to (scalar_int_mode ((scalar_int_mode::from_int) E_QImode)). Use E_QImode instead in arm_preferred_simd_mode, to fix the build. Same for HImode, SImode, HFmode and SFmode as introduced by a recent patch. 2020-10-12 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm.c (arm_preferred_simd_mode): Use E_FOOmode instead of FOOmode. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5d9c995..0b8c5fa 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28967,11 +28967,11 @@ arm_preferred_simd_mode (scalar_mode mode) if (TARGET_HAVE_MVE) switch (mode) { - case QImode: + case E_QImode: return V16QImode; - case HImode: + case E_HImode: return V8HImode; - case SImode: + case E_SImode: return V4SImode; default:; @@ -28980,9 +28980,9 @@ arm_preferred_simd_mode (scalar_mode mode) if (TARGET_HAVE_MVE_FLOAT) switch (mode) { - case HFmode: + case E_HFmode: return V8HFmode; - case SFmode: + case E_SFmode: return V4SFmode; default:;
Hi Christophe, > -----Original Message----- > From: Gcc-patches <gcc-patches-bounces@gcc.gnu.org> On Behalf Of > Christophe Lyon via Gcc-patches > Sent: 12 October 2020 12:41 > To: Dennis Zhang <Dennis.Zhang@arm.com> > Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; nd <nd@arm.com>; > gcc-patches@gcc.gnu.org; Ramana Radhakrishnan > <Ramana.Radhakrishnan@arm.com> > Subject: Re: Ping: [PATCH][Arm] Enable MVE SIMD modes for vectorization > > Hi, > > > On Thu, 8 Oct 2020 at 16:22, Christophe Lyon <christophe.lyon@linaro.org> > wrote: > > > > On Thu, 8 Oct 2020 at 16:08, Dennis Zhang <dennis.zhang@arm.com> > wrote: > > > > > > Hi Christophe, > > > > > > On 08/10/2020 14:14, Christophe Lyon wrote: > > > > Hi, > > > > > > > > > > > > On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches > > > > <gcc-patches@gcc.gnu.org> wrote: > > > >> > > > >> On 9/16/20 4:00 PM, Dennis Zhang wrote: > > > >>> Hi all, > > > >>> > > > >>> This patch enables SIMD modes for MVE auto-vectorization. > > > >>> In this patch, the integer and float MVE SIMD modes are returned by > > > >>> arm_preferred_simd_mode > (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when > > > >>> MVE or MVE_FLOAT is enabled. > > > >>> Then the expanders for auto-vectorization can be used for > generating MVE > > > >>> SIMD code. > > > >>> > > > >>> This patch also fixes bugs in MVE vreiterpretq_*.c tests which are > > > >>> revealed by the enabled MVE SIMD modes. > > > >>> The tests are for checking the MVE reinterpret intrinsics. > > > >>> There are two functions in each of the tests. The two functions > contain > > > >>> the pattern of identical code so that they are folded in icf pass. > > > >>> Because of icf, the instruction count only checks one function which > is 8. > > > >>> However when the SIMD modes are enabled, the estimation of the > code size > > > >>> becomes smaller so that inlining is applied after icf, then the > > > >>> instruction count becomes 16 which causes failure of the tests. > > > >>> Because the icf is not the expected pattern to be tested but causes > > > >>> above issues, -fno-ipa-icf is applied to the tests to avoid unstable > > > >>> instruction count. > > > >>> > > > >>> This patch is separated from > > > >>> https://gcc.gnu.org/pipermail/gcc-patches/2020- > August/552104.html > > > >>> because this part is not strongly connected to the aim of that one so > > > >>> that causing confusion. > > > >>> > > > >>> Regtested and bootstraped. > > > >>> > > > >>> Is it OK for trunk please? > > > >>> > > > >>> Thanks > > > >>> Dennis > > > >>> > > > >>> gcc/ChangeLog: > > > >>> > > > >>> 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> > > > >>> > > > >>> * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE > SIMD modes. > > > >>> > > > > > > > > Since toolchain builds work again after Jakub's divmod fix, I'm now > > > > facing another build error likely caused by this patch: > > > > In file included from > > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc- > fsf/gccsrc/gcc/coretypes.h:449:0, > > > > from > > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc- > fsf/gccsrc/gcc/config/arm/arm.c:28: > > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc- > fsf/gccsrc/gcc/config/arm/arm.c: > > > > In function 'machine_mode arm_preferred_simd_mode(scalar_mode)': > > > > ./insn-modes.h:196:71: error: temporary of non-literal type > > > > 'scalar_int_mode' in a constant expression > > > > #define QImode (scalar_int_mode ((scalar_int_mode::from_int) > E_QImode)) > > > > ^ > > > > /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc- > fsf/gccsrc/gcc/config/arm/arm.c:28970:12: > > > > note: in expansion of macro 'QImode' > > > > case QImode: > > > > > > > > and similarly for the other cases. > > > > > > > > Does the build work for you? > > > > > > > > Thanks, > > > > > > > > Christophe > > > > > > > > > > Thanks for the report. Sorry to see the error. > > > I tested it for arm-none-eabi and arm-none-linux-gnueabi targets. I > > > didn't get this error. > > > Could you please help to show the configuration you use for your build? > > > I will test and fix at once. > > > > > > > It fails on all of them for me. Does it work for you with current > > master? (r11-3720-gf18eeb6b958acd5e1590ca4a73231486b749be9b) > > > > So... I guess you are using a host with GCC more recent than 4.8.5? :-) > When I build manually on ubuntu-16.04 with gcc-5.4, the build succeeds, > and after manually building with the same environment in the compute > farm I use for validation (RHEL 7, gcc-4.8.5), I managed to reproduce the > build failure. > It's a matter of replacing > case QImode: > with > case E_QImode: > > Is the attached patch OK? Or do we instead want to revisit the minimum > gcc version required to build gcc? I'd rather go with this patch as long as it passes the usual testing. Thanks, Kyrill > > Thanks, > > Christophe > > > > > Thanks > > > Dennis
Hi Christophe, On 12/10/2020 12:40, Christophe Lyon wrote: > Hi, > > > On Thu, 8 Oct 2020 at 16:22, Christophe Lyon <christophe.lyon@linaro.org> wrote: >> >> On Thu, 8 Oct 2020 at 16:08, Dennis Zhang <dennis.zhang@arm.com> wrote: >>> >>> Hi Christophe, >>> >>> On 08/10/2020 14:14, Christophe Lyon wrote: >>>> Hi, >>>> >>>> >>>> On Tue, 6 Oct 2020 at 15:37, Dennis Zhang via Gcc-patches >>>> <gcc-patches@gcc.gnu.org> wrote: >>>>> >>>>> On 9/16/20 4:00 PM, Dennis Zhang wrote: >>>>>> Hi all, >>>>>> >>>>>> This patch enables SIMD modes for MVE auto-vectorization. >>>>>> In this patch, the integer and float MVE SIMD modes are returned by >>>>>> arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when >>>>>> MVE or MVE_FLOAT is enabled. >>>>>> Then the expanders for auto-vectorization can be used for generating MVE >>>>>> SIMD code. >>>>>> >>>>>> This patch also fixes bugs in MVE vreiterpretq_*.c tests which are >>>>>> revealed by the enabled MVE SIMD modes. >>>>>> The tests are for checking the MVE reinterpret intrinsics. >>>>>> There are two functions in each of the tests. The two functions contain >>>>>> the pattern of identical code so that they are folded in icf pass. >>>>>> Because of icf, the instruction count only checks one function which is 8. >>>>>> However when the SIMD modes are enabled, the estimation of the code size >>>>>> becomes smaller so that inlining is applied after icf, then the >>>>>> instruction count becomes 16 which causes failure of the tests. >>>>>> Because the icf is not the expected pattern to be tested but causes >>>>>> above issues, -fno-ipa-icf is applied to the tests to avoid unstable >>>>>> instruction count. >>>>>> >>>>>> This patch is separated from >>>>>> https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552104.html >>>>>> because this part is not strongly connected to the aim of that one so >>>>>> that causing confusion. >>>>>> >>>>>> Regtested and bootstraped. >>>>>> >>>>>> Is it OK for trunk please? >>>>>> >>>>>> Thanks >>>>>> Dennis >>>>>> >>>>>> gcc/ChangeLog: >>>>>> >>>>>> 2020-09-15 Dennis Zhang <dennis.zhang@arm.com> >>>>>> >>>>>> * config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes. >>>>>> >>>> >>>> Since toolchain builds work again after Jakub's divmod fix, I'm now >>>> facing another build error likely caused by this patch: >>>> In file included from >>>> /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/coretypes.h:449:0, >>>> from >>>> /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28: >>>> /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c: >>>> In function 'machine_mode arm_preferred_simd_mode(scalar_mode)': >>>> ./insn-modes.h:196:71: error: temporary of non-literal type >>>> 'scalar_int_mode' in a constant expression >>>> #define QImode (scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) >>>> ^ >>>> /tmp/2601185_2.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:28970:12: >>>> note: in expansion of macro 'QImode' >>>> case QImode: >>>> >>>> and similarly for the other cases. >>>> >>>> Does the build work for you? >>>> >>>> Thanks, >>>> >>>> Christophe >>>> >>> >>> Thanks for the report. Sorry to see the error. >>> I tested it for arm-none-eabi and arm-none-linux-gnueabi targets. I >>> didn't get this error. >>> Could you please help to show the configuration you use for your build? >>> I will test and fix at once. >>> >> >> It fails on all of them for me. Does it work for you with current >> master? (r11-3720-gf18eeb6b958acd5e1590ca4a73231486b749be9b) >> > > So... I guess you are using a host with GCC more recent than 4.8.5? :-) > When I build manually on ubuntu-16.04 with gcc-5.4, the build succeeds, > and after manually building with the same environment in the compute > farm I use for validation (RHEL 7, gcc-4.8.5), I managed to reproduce the > build failure. > It's a matter of replacing > case QImode: > with > case E_QImode: > > Is the attached patch OK? Or do we instead want to revisit the minimum > gcc version required to build gcc? > > Thanks, > > Christophe > I've tested your patch and it works with my other patches depending on this one. So I agree this patch is OK. Thanks for the fix. Bests Dennis
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dd78141519e..c50d5aca6a9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28964,6 +28964,30 @@ arm_preferred_simd_mode (scalar_mode mode) default:; } + if (TARGET_HAVE_MVE) + switch (mode) + { + case QImode: + return V16QImode; + case HImode: + return V8HImode; + case SImode: + return V4SImode; + + default:; + } + + if (TARGET_HAVE_MVE_FLOAT) + switch (mode) + { + case HFmode: + return V8HFmode; + case SFmode: + return V4SFmode; + + default:; + } + return word_mode; } diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c index f59f69734ed..2398d894861 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int8x16_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_f16 (r7, vreinterpretq_f16 (value9)); } -/* { dg-final { scan-assembler-times "vadd.f16" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.f16" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c index dac47c7e924..5a58dc6eb4c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_f32 (r7, vreinterpretq_f32 (value9)); } -/* { dg-final { scan-assembler-times "vadd.f32" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.f32" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c index edc2f2f3bc6..9ab05e95420 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int8x16_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_s16 (r7, vreinterpretq_s16 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i16" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i16" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c index 880de06a781..fbfff1fc1bb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_s32 (r7, vreinterpretq_s32 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i32" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i32" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c index b0e81542956..beb6b927deb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -42,4 +42,4 @@ foo1 (mve_pred16_t __p) return vpselq_s64 (r7, vreinterpretq_s64 (value9), __p); } -/* { dg-final { scan-assembler-times "vpsel" 8 } } */ +/* { dg-final { scan-assembler-times "vpsel" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c index a5ceebb10b9..727d89b63ee 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_s8 (r7, vreinterpretq_s8 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i8" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i8" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c index cd31c23500a..600f6d72a96 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int8x16_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_u16 (r7, vreinterpretq_u16 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i16" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i16" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c index faa66c9e1cc..d536ae825de 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_u32 (r7, vreinterpretq_u32 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i32" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i32" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c index 853b28a2aac..abc43612b91 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -42,4 +42,4 @@ foo1 (mve_pred16_t __p) return vpselq_u64 (r7, vreinterpretq_u64 (value9), __p); } -/* { dg-final { scan-assembler-times "vpsel" 8 } } */ +/* { dg-final { scan-assembler-times "vpsel" 16 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c index bdf8cd588e1..c138e5b3668 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ -/* { dg-additional-options "-O2" } */ +/* { dg-additional-options "-O2 -fno-ipa-icf" } */ #include "arm_mve.h" int16x8_t value1; @@ -41,4 +41,4 @@ foo1 () return vaddq_u8 (r7, vreinterpretq_u8 (value9)); } -/* { dg-final { scan-assembler-times "vadd.i8" 8 } } */ +/* { dg-final { scan-assembler-times "vadd.i8" 16 } } */