From patchwork Tue Apr 4 17:00:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 746886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vyFbs6rMPz9s8F for ; Wed, 5 Apr 2017 03:00:56 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="FtdDik/C"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=SvFHgN6gl1UGYVkGJ M6Ok5ou69agst3TUpjzrt1uRoofesxWBnShspLCnTfbgrK/Xn76+7Uyp0JrhDrpb 5k3DrJ+tY8xsbHg255SGpREc+Ue+YB7dLGKhBPgXT0J0hkq83h7uIcKALi6Gq+Vm b8pk+EvePpDnBbPKkULEQLf2uM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=id3atuF8JGPUzWEpXtay1a3 Mj4g=; b=FtdDik/CNSyvt3R/ju2ZN9iyW5XUskjIxxYKvtwJPPaKWws68g6o66j w4q4NIibhAq4VlpFJW5/gDWAWvmndaVcOWSEqh8io3TTIGC9bFrRhzCkAAYZTVSb 42wS6k4oFz2D/7wyH0N8zMKRpz30A4m1URzMmip0h54/KGcSLz18= Received: (qmail 75699 invoked by alias); 4 Apr 2017 17:00:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75559 invoked by uid 89); 4 Apr 2017 17:00:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Apr 2017 17:00:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 10B7C344; Tue, 4 Apr 2017 10:00:06 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4EB463F3E1; Tue, 4 Apr 2017 10:00:05 -0700 (PDT) Subject: Re: [PATCH, GCC/testsuite/ARM, stage4, ping] Compile atomic_loaddi_11 for Cortex-R5 To: "Richard Earnshaw (lists)" , Kyrill Tkachov , Ramana Radhakrishnan , "gcc-patches@gcc.gnu.org" References: <55a17848-dedc-9eec-7258-7e80708b9ed8@arm.com> <4d5a7848-e57d-38fd-5bc3-3c0c7d1c33c6@foss.arm.com> From: Thomas Preudhomme Message-ID: <53bd3df0-6158-5f1b-6e25-088cf3e8326e@foss.arm.com> Date: Tue, 4 Apr 2017 18:00:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Hi, gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does not test the changed code since ARMv7-R does not have division instructions in ARM state. This patch changes it to target Cortex-R5 processor instead which does have division instructions in ARM state. ChangeLog entry is as follows: *** gcc/testsuite/ChangeLog *** 2017-03-22 Thomas Preud'homme Ping? > > Best regards, > > Thomas > > On 23/03/17 17:09, Thomas Preudhomme wrote: >> My apologize, this works for both -march of -mcpu not cortex-r4 in RUNTESTFLAGS. >> >> ChangeLog entry is unchanged: >> >> *** gcc/testsuite/ChangeLog *** >> >> 2017-03-22 Thomas Preud'homme > >> PR target/80082 >> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of >> ARMv7-R. >> >> Best regards, >> >> Thomas >> >> On 23/03/17 16:53, Thomas Preudhomme wrote: >>> Sorry, I forgot about -march. Hold on. >>> >>> On 23/03/17 16:51, Thomas Preudhomme wrote: >>>> Please find attached an updated patch. ChangeLog entry unchanged: >>>> >>>> *** gcc/testsuite/ChangeLog *** >>>> >>>> 2017-03-22 Thomas Preud'homme >>> >>>> PR target/80082 >>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of >>>> ARMv7-R. >>>> >>>> Is this ok for stage4? >>>> >>>> Best regards, >>>> >>>> Thomas >>>> >>>> On 23/03/17 16:19, Thomas Preudhomme wrote: >>>>> Mmmh I probably need to add a dg-skip-if in there. Will respin the patch. >>>>> >>>>> Best regards, >>>>> >>>>> Thomas >>>>> >>>>> On 23/03/17 16:10, Richard Earnshaw (lists) wrote: >>>>>> On 23/03/17 16:02, Thomas Preudhomme wrote: >>>>>>> Hi, >>>>>>> >>>>>>> gcc.target/arm/atomic_loaddi_11.c testcase contributed in r246365 does >>>>>>> not test the changed code since ARMv7-R does not have division >>>>>>> instructions in ARM state. This patch changes it to target Cortex-R5 >>>>>>> processor instead which does have division instructions in ARM state. >>>>>>> >>>>>>> ChangeLog entry is as follows: >>>>>>> >>>>>>> *** gcc/testsuite/ChangeLog *** >>>>>>> >>>>>>> 2017-03-22 Thomas Preud'homme >>>>>> >>>>>>> PR target/80082 >>>>>>> * gcc.target/arm/atomic_loaddi_11.c: Target Cortex-R5 instead of >>>>>>> ARMv7-R. >>>>>>> >>>>>>> Is this ok for stage4? >>>>>>> >>>>>>> Best regards, >>>>>>> >>>>>>> Thomas >>>>>>> >>>>>>> atomic_loaddi_11_cortexr5.patch >>>>>>> >>>>>>> >>>>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c >>>>>>> b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c >>>>>>> index >>>>>>> 275669bd76356dc7c7b6a5373792d9a5089ede51..4ada2efd5f047154f2ca2fb39e9432c96ee1d42b >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> 100644 >>>>>>> --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c >>>>>>> +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c >>>>>>> @@ -1,7 +1,6 @@ >>>>>>> /* { dg-do compile } */ >>>>>>> /* { dg-require-effective-target arm_arch_v7r_ok } */ >>>>>>> -/* { dg-options "-O2" } */ >>>>>>> -/* { dg-add-options arm_arch_v7r } */ >>>>>>> +/* { dg-options "-O2 -mcpu=cortex-r5" } */ >>>>>>> >>>>>>> #include >>>>>>> >>>>>>> >>>>>> >>>>>> Will that work properly if doing multilib testing with a specific CPU >>>>>> target? >>>>>> >>>>>> R. >>>>>> diff --git a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c index 275669bd76356dc7c7b6a5373792d9a5089ede51..85c64ae68b1b1ee68466809f7f83d07ceabec575 100644 --- a/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c +++ b/gcc/testsuite/gcc.target/arm/atomic_loaddi_11.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_arch_v7r_ok } */ -/* { dg-options "-O2" } */ -/* { dg-add-options arm_arch_v7r } */ +/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" "-march=*" } { "-mcpu=cortex-r5" } } */ +/* { dg-options "-O2 -mcpu=cortex-r5" } */ #include