From patchwork Mon Aug 18 12:24:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 380991 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 57D8A1400D2 for ; Mon, 18 Aug 2014 22:27:11 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=IjaTEBk2C4kwGHynMeLQzsqE8xlwkFN1NiDNkBkFx9c 7eA+DX4gVeNUrcxmLldzUAVj51quCNpxOoJPSP/mwCgUWO13XmS4foXhd3ocKeBu lQXGVDMk21KrDrccpWalmmrKoXx8eq7GcQcULkDz509Et5W1YglLxe66EfBprFsc = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=mA01Ud+uzsqEjShTzUiRwWlohEw=; b=HeD76H2nWy4If/1OQ 0p5AFvcayuxSNrYLGDqzZK58M9CCYFfE0Sd+wjdYSqNsGHIuXh3aExsJKbWIf8x1 lqVsEoSaCTgvvg6+a8ONN0wXWpqyJb17cz+L/wJI6Plnfk4nu6lNATB8MPTUTgap ZslVavN83wTXcoLpOexRse5Oa8= Received: (qmail 32557 invoked by alias); 18 Aug 2014 12:24:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32426 invoked by uid 89); 18 Aug 2014 12:24:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Aug 2014 12:24:12 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 18 Aug 2014 13:24:09 +0100 Received: from [10.1.208.24] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 18 Aug 2014 13:24:09 +0100 Message-ID: <53F1F068.4070708@arm.com> Date: Mon, 18 Aug 2014 13:24:08 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: GCC Patches CC: Richard Earnshaw , Marcus Shawcroft Subject: [PATCH][AArch64] Use CC_Z and CC_NZ with csinc and similar instructions X-MC-Unique: 114081813240902401 X-IsSubscribed: yes Hi all, Currently for code: int foo (unsigned a, unsigned b) { int r = 0; r = a & b; if (a & b) return ++ r; return r; } we generate: foo: and w0, w0, w1 cmp w0, wzr csinc w0, wzr, w0, eq ret If we relax the csinc and similar patterns to accept the CC_Z and CC_NZ codes we can improve this to: foo: ands w0, w0, w1 csinc w0, wzr, w0, eq ret Bootstrapped and tested on aarch64-linux Ok for trunk? 2014-08-15 Kyrylo Tkachov * config/aarch64/iterators.md (CC_ZERO): New iterator. * config/aarch64/aarch64.md (*csinc2_insn): Use CC_ZERO iterator on operand 3. Rename to... (*csinc2__insn): ...This. (csinc3_insn): Use CC_ZERO iterator on operand 2. Rename to... (csinc3__insn): ...This. (*csinv3_insn): Use CC_ZERO iterator on operand 2. Rename to... (*csinv3__insn): ... This. (*csneg3_insn): Use CC_ZERO iterator on operand 2. Rename to... (*csneg3__insn): ... This. (ffs2): Update gen_csinc3_cc_insn callsite. commit 73e76eff0f99eff8d2a6b40ac4ea662a98c7c45d Author: Kyrylo Tkachov Date: Mon Aug 4 16:49:24 2014 +0100 [AArch64] Use CC_NZ in csinc pattern diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3c51fd3..568059d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2596,21 +2596,21 @@ (define_insn "aarch64_" [(set_attr "type" "crc")] ) -(define_insn "*csinc2_insn" +(define_insn "*csinc2__insn" [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator" - [(match_operand:CC 3 "cc_register" "") (const_int 0)]) + [(match_operand:CC_ZERO 3 "cc_register" "") (const_int 0)]) (match_operand:GPI 1 "register_operand" "r")))] "" "csinc\\t%0, %1, %1, %M2" [(set_attr "type" "csel")] ) -(define_insn "csinc3_insn" +(define_insn "csinc3__insn" [(set (match_operand:GPI 0 "register_operand" "=r") (if_then_else:GPI (match_operator:GPI 1 "aarch64_comparison_operator" - [(match_operand:CC 2 "cc_register" "") (const_int 0)]) + [(match_operand:CC_ZERO 2 "cc_register" "") (const_int 0)]) (plus:GPI (match_operand:GPI 3 "register_operand" "r") (const_int 1)) (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] @@ -2619,11 +2619,11 @@ (define_insn "csinc3_insn" [(set_attr "type" "csel")] ) -(define_insn "*csinv3_insn" +(define_insn "*csinv3__insn" [(set (match_operand:GPI 0 "register_operand" "=r") (if_then_else:GPI (match_operator:GPI 1 "aarch64_comparison_operator" - [(match_operand:CC 2 "cc_register" "") (const_int 0)]) + [(match_operand:CC_ZERO 2 "cc_register" "") (const_int 0)]) (not:GPI (match_operand:GPI 3 "register_operand" "r")) (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" @@ -2631,11 +2631,11 @@ (define_insn "*csinv3_insn" [(set_attr "type" "csel")] ) -(define_insn "*csneg3_insn" +(define_insn "*csneg3__insn" [(set (match_operand:GPI 0 "register_operand" "=r") (if_then_else:GPI (match_operator:GPI 1 "aarch64_comparison_operator" - [(match_operand:CC 2 "cc_register" "") (const_int 0)]) + [(match_operand:CC_ZERO 2 "cc_register" "") (const_int 0)]) (neg:GPI (match_operand:GPI 3 "register_operand" "r")) (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" @@ -2896,7 +2896,7 @@ (define_expand "ffs2" emit_insn (gen_rbit2 (operands[0], operands[1])); emit_insn (gen_clz2 (operands[0], operands[0])); - emit_insn (gen_csinc3_insn (operands[0], x, ccreg, operands[0], const0_rtx)); + emit_insn (gen_csinc3_cc_insn (operands[0], x, ccreg, operands[0], const0_rtx)); DONE; } ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 3203c3d..fe39768 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -191,6 +191,9 @@ (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) ;; Modes available for mul lane operations changing lane count. (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) +;; Iterator over CC, CC_Z, CC_NZ +(define_mode_iterator CC_ZERO [CC CC_Z CC_NZ]) + ;; ------------------------------------------------------------------ ;; Unspec enumerations for Advance SIMD. These could well go into ;; aarch64.md but for their use in int_iterators here.