From patchwork Thu Jun 12 14:08:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiong Wang X-Patchwork-Id: 359179 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9E56514007C for ; Fri, 13 Jun 2014 00:09:36 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=v+fFdowTm/UkudsUchbwppvXCZRG4T5dhxCo55XDt5GfBT 8PxKt3QZmppuHfQ0SCet8QltIyUrQ8OVagPd/I0p3eazI5hxSfpT0yhdLZvW8yah +CLqeC8qrcfZ2wBYAaqW1kR404nRUqGYFgCEHW5XJW3HRhGpo+BiSYyHoCZPI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=1sfUwnZNKYOj9dUxeaPc62ejqds=; b=u/fPmKc7k3rSmpQJcj2q rIMl2s3eomCeLbYJsEtA7j7qNOMXsnQ8EP/lC7mUbQibydTSnqgpN2YP/WUBU2N7 vaePfeeIFKtPLdIC0G7fEpCgviCFNe3TJyQep48GdOKprr3ZvIa9MzqasThu+S5p 6S5HCmLGn6Z2HVnk0iA/bTo= Received: (qmail 20709 invoked by alias); 12 Jun 2014 14:09:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20548 invoked by uid 89); 12 Jun 2014 14:09:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 12 Jun 2014 14:09:07 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 12 Jun 2014 15:09:02 +0100 Received: from [10.1.205.157] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 12 Jun 2014 15:08:55 +0100 Message-ID: <5399B47B.4080500@arm.com> Date: Thu, 12 Jun 2014 15:08:59 +0100 From: Jiong Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.1 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [PATCH][AArch64] Add predicate for storewb_pair/loadwb_pair X-MC-Unique: 114061215090202001 X-IsSubscribed: yes This patch add predicate for storewb_pair/loadwb_pair, because aarch64 register pair push and pop instructions only accept constant offset within certain range. OK for trunk? Thanks. gcc/ChangeLog: 2014-06-12 Renlin Li * config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to 'aarch64_offset_7bit_signed_scaled_p', remove static and use it . * config/aarch64/aarch64-protos.h (aarch64_offset_7bit_signed_scaled_p): New Declaration. * config/aarch64/predicates.md (aarch64_mem_pair_offset): New predicate. * config/aarch64/aarch64.md (loadwb_pair): Use aarch64_mem_pair_offset. (storewb_pair): Likewise. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 68d488d..d39ecc5 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -193,6 +193,7 @@ bool aarch64_modes_tieable_p (enum machine_mode mode1, bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode); bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context, enum machine_mode); +bool aarch64_offset_7bit_signed_scaled_p (enum machine_mode, HOST_WIDE_INT); char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode); char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned); bool aarch64_pad_arg_upward (enum machine_mode, const_tree); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f69457a..192caf4 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3122,8 +3122,9 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x, return false; } -static inline bool -offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset) +bool +aarch64_offset_7bit_signed_scaled_p (enum machine_mode mode, + HOST_WIDE_INT offset) { return (offset >= -64 * GET_MODE_SIZE (mode) && offset < 64 * GET_MODE_SIZE (mode) @@ -3195,12 +3196,12 @@ aarch64_classify_address (struct aarch64_address_info *info, We conservatively require an offset representable in either mode. */ if (mode == TImode || mode == TFmode) - return (offset_7bit_signed_scaled_p (mode, offset) + return (aarch64_offset_7bit_signed_scaled_p (mode, offset) && offset_9bit_signed_unscaled_p (mode, offset)); if (outer_code == PARALLEL) return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8) - && offset_7bit_signed_scaled_p (mode, offset)); + && aarch64_offset_7bit_signed_scaled_p (mode, offset)); else return (offset_9bit_signed_unscaled_p (mode, offset) || offset_12bit_unsigned_scaled_p (mode, offset)); @@ -3255,12 +3256,12 @@ aarch64_classify_address (struct aarch64_address_info *info, We conservatively require an offset representable in either mode. */ if (mode == TImode || mode == TFmode) - return (offset_7bit_signed_scaled_p (mode, offset) + return (aarch64_offset_7bit_signed_scaled_p (mode, offset) && offset_9bit_signed_unscaled_p (mode, offset)); if (outer_code == PARALLEL) return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8) - && offset_7bit_signed_scaled_p (mode, offset)); + && aarch64_offset_7bit_signed_scaled_p (mode, offset)); else return offset_9bit_signed_unscaled_p (mode, offset); } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index fec2ea8..e15747f 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -949,7 +949,7 @@ [(parallel [(set (match_operand:P 0 "register_operand" "=k") (plus:P (match_operand:P 1 "register_operand" "0") - (match_operand:P 4 "const_int_operand" "n"))) + (match_operand:P 4 "aarch64_mem_pair_offset" "n"))) (set (match_operand:GPI 2 "register_operand" "=r") (mem:GPI (plus:P (match_dup 1) (match_dup 4)))) @@ -967,7 +967,7 @@ [(parallel [(set (match_operand:P 0 "register_operand" "=&k") (plus:P (match_operand:P 1 "register_operand" "0") - (match_operand:P 4 "const_int_operand" "n"))) + (match_operand:P 4 "aarch64_mem_pair_offset" "n"))) (set (mem:GPI (plus:P (match_dup 0) (match_dup 4))) (match_operand:GPI 2 "register_operand" "r")) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 2702a3c..478de11 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -123,6 +123,10 @@ (match_test "INTVAL (op) != 0 && (unsigned) exact_log2 (INTVAL (op)) < 64"))) +(define_predicate "aarch64_mem_pair_offset" + (and (match_code "const_int") + (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))"))) + (define_predicate "aarch64_mem_pair_operand" (and (match_code "mem") (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,