From patchwork Thu May 29 09:43:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 353713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 975A41400CF for ; Thu, 29 May 2014 19:43:19 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; q=dns; s=default; b=wQvpGdMslph+48GXV z4vtql8d8bRhnH2TKkHyqPRiXyQ/weUqilx8xEBc4AAUf1YFD2w9aVAHxPGLsbYh R+CqbX+Y0O/KutEhUWxk7aswqRZA5tJVRavi07ePPTi1HSOKxQBqpfhpsbRfcrtG TVls+fUYFOIJmvXgIcfmLdMV0A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:references :in-reply-to:content-type; s=default; bh=yNRNBQ24eo1INcUhm2lbkh9 MFYw=; b=FtyvCsvzHKT81JQWV23UGn/kx10hT22zP92X+r2Ck1aLlKJQ2GVv2Y9 7cOdNLOn18FHxpaDDraIS/FLRbHsrhDzGas6HiahX2LuKln65NbT+OgPZPTgKtGb IgvIfLSQRrOd24nmKRoR5EDN3l6d+LK3D/FNms+LDD159V+SZDis= Received: (qmail 28232 invoked by alias); 29 May 2014 09:43:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28222 invoked by uid 89); 29 May 2014 09:43:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 May 2014 09:43:09 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 29 May 2014 10:43:05 +0100 Received: from [10.1.208.33] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 29 May 2014 10:43:02 +0100 Message-ID: <53870126.2080002@arm.com> Date: Thu, 29 May 2014 10:43:02 +0100 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:15.0) Gecko/20120907 Thunderbird/15.0.1 MIME-Version: 1.0 To: Christophe Lyon , Jeff Law , "gcc-patches@gcc.gnu.org" , rdsandiford@googlemail.com Subject: Re: RFA: cache enabled attribute by insn code References: <87k39gkgq0.fsf@talisman.default> <537B95E9.1010203@redhat.com> <87iop0i13e.fsf@talisman.default> <537F9126.5080904@redhat.com> <87zji31fh7.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> <87r43f1f1e.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> <87ioor1cr8.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> In-Reply-To: <87ioor1cr8.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> X-MC-Unique: 114052910430522201 X-IsSubscribed: yes On 27/05/14 16:07, Richard Sandiford wrote: > Richard Sandiford writes: >> Richard Sandiford writes: >>> Does the following patch help? >> >> Bah, it won't of course: %i1 needs to be the operator. > > Here's v2. I tested that it worked for simple tests like: > > int f1 (int x, int y) { return x + (y << 4); } > int f2 (int x, int y) { return x - (y << 4); } > int f3 (int x, int y) { return x & (y << 4); } > int f4 (int x, int y) { return x | (y << 4); } > int f5 (int x, int y) { return x ^ (y << 4); } > int f6 (int x, int y) { return (y << 4) - x; } > int g1 (int x, int y, int z) { return x + (y << z); } > int g2 (int x, int y, int z) { return x - (y << z); } > int g3 (int x, int y, int z) { return x & (y << z); } > int g4 (int x, int y, int z) { return x | (y << z); } > int g5 (int x, int y, int z) { return x ^ (y << z); } > int g6 (int x, int y, int z) { return (y << z) - x; } > > as well as the testcase. > > Thanks, > Richard > > > gcc/ > * config/arm/iterators.md (shiftable_ops): New code iterator. > (t2_binop0, arith_shift_insn): New code attributes. > * config/arm/arm.md (insn_enabled): Delete. > (enabled): Remove insn_enabled test. > (*arith_shiftsi): Split out... > (*arith_multsi): ...this pattern and remove insn_enabled attribute. > Thanks, Richard. I've tweaked this as followed and committed it. I now consider "shift_operator" in the arm backend deprecated. We should be moving towards using shift_nomul_operator. There's one final wart still to be handled, though. 'rotate' can only take an immediate operand, not a register. We can currently deal with this, but it's not clean in terms of constraint handling. I'll see if I can fix this up sometime, but not today. R. 2014-05-29 Richard Earnshaw Richard Sandiford * arm/iterators.md (shiftable_ops): New code iterator. (t2_binop0, arith_shift_insn): New code attributes. * arm/predicates.md (shift_nomul_operator): New predicate. * arm/arm.md (insn_enabled): Delete. (enabled): Remove insn_enabled test. (*arith_shiftsi): Delete. Replace with ... (*_multsi): ... new pattern. (*_shiftsi): ... new pattern. * config/arm/arm.c (arm_print_operand): Handle operand format 'b'. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index ccad548..b514757 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -21271,7 +21271,15 @@ arm_print_condition (FILE *stream) } -/* If CODE is 'd', then the X is a condition operand and the instruction +/* Globally reserved letters: acln + Puncutation letters currently used: @_|?().!# + Lower case letters currently used: bcdefhimpqtvwxyz + Upper case letters currently used: ABCDFGHJKLMNOPQRSTU + Letters previously used, but now deprecated/obsolete: sVWXYZ. + + Note that the global reservation for 'c' is only for CONSTANT_ADDRESS_P. + + If CODE is 'd', then the X is a condition operand and the instruction should only be executed if the condition is true. if CODE is 'D', then the X is a condition operand and the instruction should only be executed if the condition is false: however, if the mode @@ -21411,6 +21419,19 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; + case 'b': + /* Print the log2 of a CONST_INT. */ + { + HOST_WIDE_INT val; + + if (!CONST_INT_P (x) + || (val = exact_log2 (INTVAL (x) & 0xffffffff)) < 0) + output_operand_lossage ("Unsupported operand for code '%c'", code); + else + fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); + } + return; + case 'L': /* The low 16 bits of an immediate constant. */ fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 348a89c..cd7495f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -200,17 +200,9 @@ (const_string "yes")] (const_string "no"))) -; Allows an insn to disable certain alternatives for reasons other than -; arch support. -(define_attr "insn_enabled" "no,yes" - (const_string "yes")) - ; Enable all alternatives that are both arch_enabled and insn_enabled. (define_attr "enabled" "no,yes" - (cond [(eq_attr "insn_enabled" "no") - (const_string "no") - - (and (eq_attr "predicable_short_it" "no") + (cond [(and (eq_attr "predicable_short_it" "no") (and (eq_attr "predicated" "yes") (match_test "arm_restrict_it"))) (const_string "no") @@ -9876,38 +9868,34 @@ ;; Patterns to allow combination of arithmetic, cond code and shifts -(define_insn "*arith_shiftsi" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") - (match_operator:SI 1 "shiftable_operator" - [(match_operator:SI 3 "shift_operator" - [(match_operand:SI 4 "s_register_operand" "r,r,r,r") - (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")]) - (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))] +(define_insn "*_multsi" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (shiftable_ops:SI + (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "power_of_two_operand" "")) + (match_operand:SI 1 "s_register_operand" "rk,")))] "TARGET_32BIT" - "%i1%?\\t%0, %2, %4%S3" + "%?\\t%0, %1, %2, lsl %b3" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "shift" "4") + (set_attr "arch" "a,t2") + (set_attr "type" "alu_shift_imm")]) + +(define_insn "*_shiftsi" + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (shiftable_ops:SI + (match_operator:SI 2 "shift_nomul_operator" + [(match_operand:SI 3 "s_register_operand" "r,r,r") + (match_operand:SI 4 "shift_amount_operand" "M,M,r")]) + (match_operand:SI 1 "s_register_operand" "rk,,rk")))] + "TARGET_32BIT && GET_CODE (operands[3]) != MULT" + "%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "shift" "4") - (set_attr "arch" "a,t2,t2,a") - ;; Thumb2 doesn't allow the stack pointer to be used for - ;; operand1 for all operations other than add and sub. In this case - ;; the minus operation is a candidate for an rsub and hence needs - ;; to be disabled. - ;; We have to make sure to disable the fourth alternative if - ;; the shift_operator is MULT, since otherwise the insn will - ;; also match a multiply_accumulate pattern and validate_change - ;; will allow a replacement of the constant with a register - ;; despite the checks done in shift_operator. - (set_attr_alternative "insn_enabled" - [(const_string "yes") - (if_then_else - (match_operand:SI 1 "add_operator" "") - (const_string "yes") (const_string "no")) - (const_string "yes") - (if_then_else - (match_operand:SI 3 "mult_operator" "") - (const_string "no") (const_string "yes"))]) - (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_imm,alu_shift_reg")]) + (set_attr "arch" "a,t2,a") + (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index aebab93..1c41c6d 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -191,6 +191,20 @@ ;; Right shifts (define_code_iterator rshifts [ashiftrt lshiftrt]) +;; Binary operators whose second operand can be shifted. +(define_code_iterator shiftable_ops [plus minus ior xor and]) + +;; plus and minus are the only shiftable_ops for which Thumb2 allows +;; a stack pointer opoerand. The minus operation is a candidate for an rsub +;; and hence only plus is supported. +(define_code_attr t2_binop0 + [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) + +;; The instruction to use when a shiftable_ops has a shift operation as +;; its first operand. +(define_code_attr arith_shift_insn + [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) + ;;---------------------------------------------------------------------------- ;; Int iterators ;;---------------------------------------------------------------------------- diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index d74fcb3..032808c 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -291,6 +291,15 @@ || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) (match_test "mode == GET_MODE (op)"))) +(define_special_predicate "shift_nomul_operator" + (and (ior (and (match_code "rotate") + (match_test "CONST_INT_P (XEXP (op, 1)) + && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")) + (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") + (match_test "!CONST_INT_P (XEXP (op, 1)) + || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) + (match_test "mode == GET_MODE (op)"))) + ;; True for shift operators which can be used with saturation instructions. (define_special_predicate "sat_shift_operator" (and (ior (and (match_code "mult")