| Message ID | 53582351.4060608@arm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Apr 23, 2014 at 9:32 PM, Alan Lawrence <alan.lawrence@arm.com> wrote: > Final patch in series, adds new tests of the ARM EXT Intrinsics, that also > check > the execution results, reusing the test bodies introduced into AArch64 in > the > first patch. (These tests subsume the autogenerated ones in > testsuite/gcc.target/arm/neon/ that only check assembler output.) > > Tests use gcc.target/arm/simd/simd.exp from corresponding patch for ZIP > Intrinsics http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01500.html, will > commit that first. > > All tests passing on arm-none-eabi. Ok if no regressions. Thanks, Ramana > > gcc/testsuite/ChangeLog: > 2014-04-23 Alan Lawrence <alan.lawrence@arm.com> > > gcc.target/arm/simd/vextQf32.c: New file. > gcc.target/arm/simd/vextQp16.c: New file. > gcc.target/arm/simd/vextQp8.c: New file. > gcc.target/arm/simd/vextQs16.c: New file. > gcc.target/arm/simd/vextQs32.c: New file. > gcc.target/arm/simd/vextQs64.c: New file. > gcc.target/arm/simd/vextQs8.c: New file. > gcc.target/arm/simd/vextQu16.c: New file. > gcc.target/arm/simd/vextQu32.c: New file. > gcc.target/arm/simd/vextQu64.c: New file. > gcc.target/arm/simd/vextQu8.c: New file. > gcc.target/arm/simd/vextQp64.c: New file. > gcc.target/arm/simd/vextf32.c: New file. > gcc.target/arm/simd/vextp16.c: New file. > gcc.target/arm/simd/vextp8.c: New file. > gcc.target/arm/simd/vexts16.c: New file. > gcc.target/arm/simd/vexts32.c: New file. > gcc.target/arm/simd/vexts64.c: New file. > gcc.target/arm/simd/vexts8.c: New file. > gcc.target/arm/simd/vextu16.c: New file. > gcc.target/arm/simd/vextu32.c: New file. > gcc.target/arm/simd/vextu64.c: New file. > gcc.target/arm/simd/vextu8.c: New file. > gcc.target/arm/simd/vextp64.c: New file. > > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32.c > b/gcc/testsuite/gcc.target/arm/simd/vextQf32.c > new file mode 100644 > index 0000000..c1da6d3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQf32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_f32.x" > + > +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 3 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16.c > b/gcc/testsuite/gcc.target/arm/simd/vextQp16.c > new file mode 100644 > index 0000000..adc0861 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQp16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_p16.x" > + > +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 7 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64.c > b/gcc/testsuite/gcc.target/arm/simd/vextQp64.c > new file mode 100644 > index 0000000..e8b688d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64.c > @@ -0,0 +1,33 @@ > +/* Test the `vextQp64' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_crypto_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_crypto } */ > + > +#include "arm_neon.h" > + > +extern void abort (void); > + > +poly64x2_t > +test_vextq_p64_1 (poly64x2_t a, poly64x2_t b) > +{ > + return vextq_p64(a, b, 1); > +} > + > +int > +main (int argc, char **argv) > +{ > + int i, off; > + poly64x2_t in1 = {0, 1}; > + poly64x2_t in2 = {2, 3}; > + poly64x2_t actual = test_vextq_p64_1 (in1, in2); > + for (i = 0; i < 2; i++) > + if (actual[i] != i + 1) > + abort (); > + > + return 0; > +} > + > +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8.c > b/gcc/testsuite/gcc.target/arm/simd/vextQp8.c > new file mode 100644 > index 0000000..5f2cc53 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQp8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_p8.x" > + > +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 15 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16.c > b/gcc/testsuite/gcc.target/arm/simd/vextQs16.c > new file mode 100644 > index 0000000..c0d791d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQs16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_s16.x" > + > +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 7 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32.c > b/gcc/testsuite/gcc.target/arm/simd/vextQs32.c > new file mode 100644 > index 0000000..ed5b210 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQs32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_s32.x" > + > +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 3 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64.c > b/gcc/testsuite/gcc.target/arm/simd/vextQs64.c > new file mode 100644 > index 0000000..dbbee47 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQs64' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_s64.x" > + > +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8.c > b/gcc/testsuite/gcc.target/arm/simd/vextQs8.c > new file mode 100644 > index 0000000..0ebdce3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQs8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_s8.x" > + > +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 15 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16.c > b/gcc/testsuite/gcc.target/arm/simd/vextQu16.c > new file mode 100644 > index 0000000..136f2b8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQu16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_u16.x" > + > +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 7 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32.c > b/gcc/testsuite/gcc.target/arm/simd/vextQu32.c > new file mode 100644 > index 0000000..66ce035 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQu32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_u32.x" > + > +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 3 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64.c > b/gcc/testsuite/gcc.target/arm/simd/vextQu64.c > new file mode 100644 > index 0000000..ebe4abd > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQu64' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_u64.x" > + > +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8.c > b/gcc/testsuite/gcc.target/arm/simd/vextQu8.c > new file mode 100644 > index 0000000..432ac0a > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8.c > @@ -0,0 +1,12 @@ > +/* Test the `vextQu8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/extq_u8.x" > + > +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, > \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 15 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32.c > b/gcc/testsuite/gcc.target/arm/simd/vextf32.c > new file mode 100644 > index 0000000..99e0bad > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextf32.c > @@ -0,0 +1,12 @@ > +/* Test the `vextf32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_f32.x" > + > +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16.c > b/gcc/testsuite/gcc.target/arm/simd/vextp16.c > new file mode 100644 > index 0000000..00695bf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextp16.c > @@ -0,0 +1,12 @@ > +/* Test the `vextp16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_p16.x" > + > +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 3 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64.c > b/gcc/testsuite/gcc.target/arm/simd/vextp64.c > new file mode 100644 > index 0000000..8783e16 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextp64.c > @@ -0,0 +1,26 @@ > +/* Test the `vextp64' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_crypto_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_crypto } */ > + > +#include "arm_neon.h" > + > +extern void abort (void); > + > +int > +main (int argc, char **argv) > +{ > + int i; > + poly64x1_t in1 = {0}; > + poly64x1_t in2 = {1}; > + poly64x1_t actual = vext_p64 (in1, in2, 0); > + if (actual != in1) > + abort (); > + > + return 0; > +} > + > +/* Don't scan assembler for vext - it can be optimized into a move from r0. > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8.c > b/gcc/testsuite/gcc.target/arm/simd/vextp8.c > new file mode 100644 > index 0000000..2ba72c1 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextp8.c > @@ -0,0 +1,12 @@ > +/* Test the `vextp8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_p8.x" > + > +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 7 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16.c > b/gcc/testsuite/gcc.target/arm/simd/vexts16.c > new file mode 100644 > index 0000000..4fa57d6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vexts16.c > @@ -0,0 +1,12 @@ > +/* Test the `vexts16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_s16.x" > + > +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 3 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32.c > b/gcc/testsuite/gcc.target/arm/simd/vexts32.c > new file mode 100644 > index 0000000..3cd5936 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vexts32.c > @@ -0,0 +1,12 @@ > +/* Test the `vexts32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_s32.x" > + > +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64.c > b/gcc/testsuite/gcc.target/arm/simd/vexts64.c > new file mode 100644 > index 0000000..7bb2012 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vexts64.c > @@ -0,0 +1,12 @@ > +/* Test the `vexts64' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_s64.x" > + > +/* Don't scan assembler for vext - it can be optimized into a move from r0. > */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8.c > b/gcc/testsuite/gcc.target/arm/simd/vexts8.c > new file mode 100644 > index 0000000..194e198 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vexts8.c > @@ -0,0 +1,12 @@ > +/* Test the `vexts8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_s8.x" > + > +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 7 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16.c > b/gcc/testsuite/gcc.target/arm/simd/vextu16.c > new file mode 100644 > index 0000000..f69c2bd > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextu16.c > @@ -0,0 +1,12 @@ > +/* Test the `vextu16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_u16.x" > + > +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 3 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32.c > b/gcc/testsuite/gcc.target/arm/simd/vextu32.c > new file mode 100644 > index 0000000..b76e383 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextu32.c > @@ -0,0 +1,12 @@ > +/* Test the `vextu32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_u32.x" > + > +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64.c > b/gcc/testsuite/gcc.target/arm/simd/vextu64.c > new file mode 100644 > index 0000000..39ffc56 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextu64.c > @@ -0,0 +1,12 @@ > +/* Test the `vextu64' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_u64.x" > + > +/* Don't scan assembler for vext - it can be optimized into a move from r0. > */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8.c > b/gcc/testsuite/gcc.target/arm/simd/vextu8.c > new file mode 100644 > index 0000000..a9d62b3 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vextu8.c > @@ -0,0 +1,12 @@ > +/* Test the `vextu8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O3 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/ext_u8.x" > + > +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, > \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 > \]+\)?\n" 7 } } */ > +/* { dg-final { cleanup-saved-temps } } */
I've just committed this as revision 211059, with the change of adding a _1 suffix to the names of all the new tests (as per standard testsuite convention). All passed on arm-none-eabi and armeb-none-eabi. Cheers, Alan Ramana Radhakrishnan wrote: > On Wed, Apr 23, 2014 at 9:32 PM, Alan Lawrence <alan.lawrence@arm.com> wrote: >> Final patch in series, adds new tests of the ARM EXT Intrinsics, that also >> check >> the execution results, reusing the test bodies introduced into AArch64 in >> the >> first patch. (These tests subsume the autogenerated ones in >> testsuite/gcc.target/arm/neon/ that only check assembler output.) >> >> Tests use gcc.target/arm/simd/simd.exp from corresponding patch for ZIP >> Intrinsics http://gcc.gnu.org/ml/gcc-patches/2014-03/msg01500.html, will >> commit that first. >> >> All tests passing on arm-none-eabi. > > > Ok if no regressions. > > Thanks, > Ramana >> gcc/testsuite/ChangeLog: >> 2014-04-23 Alan Lawrence <alan.lawrence@arm.com> >> >> gcc.target/arm/simd/vextQf32.c: New file. >> gcc.target/arm/simd/vextQp16.c: New file. >> gcc.target/arm/simd/vextQp8.c: New file. >> gcc.target/arm/simd/vextQs16.c: New file. >> gcc.target/arm/simd/vextQs32.c: New file. >> gcc.target/arm/simd/vextQs64.c: New file. >> gcc.target/arm/simd/vextQs8.c: New file. >> gcc.target/arm/simd/vextQu16.c: New file. >> gcc.target/arm/simd/vextQu32.c: New file. >> gcc.target/arm/simd/vextQu64.c: New file. >> gcc.target/arm/simd/vextQu8.c: New file. >> gcc.target/arm/simd/vextQp64.c: New file. >> gcc.target/arm/simd/vextf32.c: New file. >> gcc.target/arm/simd/vextp16.c: New file. >> gcc.target/arm/simd/vextp8.c: New file. >> gcc.target/arm/simd/vexts16.c: New file. >> gcc.target/arm/simd/vexts32.c: New file. >> gcc.target/arm/simd/vexts64.c: New file. >> gcc.target/arm/simd/vexts8.c: New file. >> gcc.target/arm/simd/vextu16.c: New file. >> gcc.target/arm/simd/vextu32.c: New file. >> gcc.target/arm/simd/vextu64.c: New file. >> gcc.target/arm/simd/vextu8.c: New file. >> gcc.target/arm/simd/vextp64.c: New file. >> >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQf32.c >> new file mode 100644 >> index 0000000..c1da6d3 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQf32' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_f32.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 3 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQp16.c >> new file mode 100644 >> index 0000000..adc0861 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQp16' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_p16.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 7 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQp64.c >> new file mode 100644 >> index 0000000..e8b688d >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64.c >> @@ -0,0 +1,33 @@ >> +/* Test the `vextQp64' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_crypto_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_crypto } */ >> + >> +#include "arm_neon.h" >> + >> +extern void abort (void); >> + >> +poly64x2_t >> +test_vextq_p64_1 (poly64x2_t a, poly64x2_t b) >> +{ >> + return vextq_p64(a, b, 1); >> +} >> + >> +int >> +main (int argc, char **argv) >> +{ >> + int i, off; >> + poly64x2_t in1 = {0, 1}; >> + poly64x2_t in2 = {2, 3}; >> + poly64x2_t actual = test_vextq_p64_1 (in1, in2); >> + for (i = 0; i < 2; i++) >> + if (actual[i] != i + 1) >> + abort (); >> + >> + return 0; >> +} >> + >> +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 1 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQp8.c >> new file mode 100644 >> index 0000000..5f2cc53 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQp8' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_p8.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 15 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQs16.c >> new file mode 100644 >> index 0000000..c0d791d >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQs16' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_s16.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 7 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQs32.c >> new file mode 100644 >> index 0000000..ed5b210 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQs32' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_s32.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 3 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQs64.c >> new file mode 100644 >> index 0000000..dbbee47 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQs64' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_s64.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 1 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQs8.c >> new file mode 100644 >> index 0000000..0ebdce3 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQs8' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_s8.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 15 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQu16.c >> new file mode 100644 >> index 0000000..136f2b8 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQu16' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_u16.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 7 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQu32.c >> new file mode 100644 >> index 0000000..66ce035 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQu32' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_u32.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 3 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQu64.c >> new file mode 100644 >> index 0000000..ebe4abd >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQu64' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_u64.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 1 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8.c >> b/gcc/testsuite/gcc.target/arm/simd/vextQu8.c >> new file mode 100644 >> index 0000000..432ac0a >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextQu8' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/extq_u8.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, >> \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 15 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32.c >> b/gcc/testsuite/gcc.target/arm/simd/vextf32.c >> new file mode 100644 >> index 0000000..99e0bad >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextf32.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextf32' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_f32.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 1 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16.c >> b/gcc/testsuite/gcc.target/arm/simd/vextp16.c >> new file mode 100644 >> index 0000000..00695bf >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextp16.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextp16' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_p16.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 3 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64.c >> b/gcc/testsuite/gcc.target/arm/simd/vextp64.c >> new file mode 100644 >> index 0000000..8783e16 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextp64.c >> @@ -0,0 +1,26 @@ >> +/* Test the `vextp64' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_crypto_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_crypto } */ >> + >> +#include "arm_neon.h" >> + >> +extern void abort (void); >> + >> +int >> +main (int argc, char **argv) >> +{ >> + int i; >> + poly64x1_t in1 = {0}; >> + poly64x1_t in2 = {1}; >> + poly64x1_t actual = vext_p64 (in1, in2, 0); >> + if (actual != in1) >> + abort (); >> + >> + return 0; >> +} >> + >> +/* Don't scan assembler for vext - it can be optimized into a move from r0. >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8.c >> b/gcc/testsuite/gcc.target/arm/simd/vextp8.c >> new file mode 100644 >> index 0000000..2ba72c1 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextp8.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextp8' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_p8.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 7 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16.c >> b/gcc/testsuite/gcc.target/arm/simd/vexts16.c >> new file mode 100644 >> index 0000000..4fa57d6 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vexts16.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vexts16' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_s16.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 3 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32.c >> b/gcc/testsuite/gcc.target/arm/simd/vexts32.c >> new file mode 100644 >> index 0000000..3cd5936 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vexts32.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vexts32' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_s32.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 1 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64.c >> b/gcc/testsuite/gcc.target/arm/simd/vexts64.c >> new file mode 100644 >> index 0000000..7bb2012 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vexts64.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vexts64' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_s64.x" >> + >> +/* Don't scan assembler for vext - it can be optimized into a move from r0. >> */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8.c >> b/gcc/testsuite/gcc.target/arm/simd/vexts8.c >> new file mode 100644 >> index 0000000..194e198 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vexts8.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vexts8' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_s8.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 7 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16.c >> b/gcc/testsuite/gcc.target/arm/simd/vextu16.c >> new file mode 100644 >> index 0000000..f69c2bd >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextu16.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextu16' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_u16.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 3 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32.c >> b/gcc/testsuite/gcc.target/arm/simd/vextu32.c >> new file mode 100644 >> index 0000000..b76e383 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextu32.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextu32' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_u32.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 1 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64.c >> b/gcc/testsuite/gcc.target/arm/simd/vextu64.c >> new file mode 100644 >> index 0000000..39ffc56 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextu64.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextu64' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_u64.x" >> + >> +/* Don't scan assembler for vext - it can be optimized into a move from r0. >> */ >> +/* { dg-final { cleanup-saved-temps } } */ >> diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8.c >> b/gcc/testsuite/gcc.target/arm/simd/vextu8.c >> new file mode 100644 >> index 0000000..a9d62b3 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/arm/simd/vextu8.c >> @@ -0,0 +1,12 @@ >> +/* Test the `vextu8' ARM Neon intrinsic. */ >> + >> +/* { dg-do run } */ >> +/* { dg-require-effective-target arm_neon_ok } */ >> +/* { dg-options "-save-temps -O3 -fno-inline" } */ >> +/* { dg-add-options arm_neon } */ >> + >> +#include "arm_neon.h" >> +#include "../../aarch64/simd/ext_u8.x" >> + >> +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, >> \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 >> \]+\)?\n" 7 } } */ >> +/* { dg-final { cleanup-saved-temps } } */ >
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32.c b/gcc/testsuite/gcc.target/arm/simd/vextQf32.c new file mode 100644 index 0000000..c1da6d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32.c @@ -0,0 +1,12 @@ +/* Test the `vextQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_f32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16.c b/gcc/testsuite/gcc.target/arm/simd/vextQp16.c new file mode 100644 index 0000000..adc0861 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16.c @@ -0,0 +1,12 @@ +/* Test the `vextQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_p16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64.c b/gcc/testsuite/gcc.target/arm/simd/vextQp64.c new file mode 100644 index 0000000..e8b688d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64.c @@ -0,0 +1,33 @@ +/* Test the `vextQp64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +extern void abort (void); + +poly64x2_t +test_vextq_p64_1 (poly64x2_t a, poly64x2_t b) +{ + return vextq_p64(a, b, 1); +} + +int +main (int argc, char **argv) +{ + int i, off; + poly64x2_t in1 = {0, 1}; + poly64x2_t in2 = {2, 3}; + poly64x2_t actual = test_vextq_p64_1 (in1, in2); + for (i = 0; i < 2; i++) + if (actual[i] != i + 1) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8.c b/gcc/testsuite/gcc.target/arm/simd/vextQp8.c new file mode 100644 index 0000000..5f2cc53 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8.c @@ -0,0 +1,12 @@ +/* Test the `vextQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_p8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16.c b/gcc/testsuite/gcc.target/arm/simd/vextQs16.c new file mode 100644 index 0000000..c0d791d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16.c @@ -0,0 +1,12 @@ +/* Test the `vextQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32.c b/gcc/testsuite/gcc.target/arm/simd/vextQs32.c new file mode 100644 index 0000000..ed5b210 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32.c @@ -0,0 +1,12 @@ +/* Test the `vextQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64.c b/gcc/testsuite/gcc.target/arm/simd/vextQs64.c new file mode 100644 index 0000000..dbbee47 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64.c @@ -0,0 +1,12 @@ +/* Test the `vextQs64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s64.x" + +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8.c b/gcc/testsuite/gcc.target/arm/simd/vextQs8.c new file mode 100644 index 0000000..0ebdce3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8.c @@ -0,0 +1,12 @@ +/* Test the `vextQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16.c b/gcc/testsuite/gcc.target/arm/simd/vextQu16.c new file mode 100644 index 0000000..136f2b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16.c @@ -0,0 +1,12 @@ +/* Test the `vextQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32.c b/gcc/testsuite/gcc.target/arm/simd/vextQu32.c new file mode 100644 index 0000000..66ce035 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32.c @@ -0,0 +1,12 @@ +/* Test the `vextQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64.c b/gcc/testsuite/gcc.target/arm/simd/vextQu64.c new file mode 100644 index 0000000..ebe4abd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64.c @@ -0,0 +1,12 @@ +/* Test the `vextQu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u64.x" + +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8.c b/gcc/testsuite/gcc.target/arm/simd/vextQu8.c new file mode 100644 index 0000000..432ac0a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8.c @@ -0,0 +1,12 @@ +/* Test the `vextQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32.c b/gcc/testsuite/gcc.target/arm/simd/vextf32.c new file mode 100644 index 0000000..99e0bad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextf32.c @@ -0,0 +1,12 @@ +/* Test the `vextf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_f32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16.c b/gcc/testsuite/gcc.target/arm/simd/vextp16.c new file mode 100644 index 0000000..00695bf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextp16.c @@ -0,0 +1,12 @@ +/* Test the `vextp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_p16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64.c b/gcc/testsuite/gcc.target/arm/simd/vextp64.c new file mode 100644 index 0000000..8783e16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextp64.c @@ -0,0 +1,26 @@ +/* Test the `vextp64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +extern void abort (void); + +int +main (int argc, char **argv) +{ + int i; + poly64x1_t in1 = {0}; + poly64x1_t in2 = {1}; + poly64x1_t actual = vext_p64 (in1, in2, 0); + if (actual != in1) + abort (); + + return 0; +} + +/* Don't scan assembler for vext - it can be optimized into a move from r0. +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8.c b/gcc/testsuite/gcc.target/arm/simd/vextp8.c new file mode 100644 index 0000000..2ba72c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextp8.c @@ -0,0 +1,12 @@ +/* Test the `vextp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_p8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16.c b/gcc/testsuite/gcc.target/arm/simd/vexts16.c new file mode 100644 index 0000000..4fa57d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts16.c @@ -0,0 +1,12 @@ +/* Test the `vexts16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32.c b/gcc/testsuite/gcc.target/arm/simd/vexts32.c new file mode 100644 index 0000000..3cd5936 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts32.c @@ -0,0 +1,12 @@ +/* Test the `vexts32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64.c b/gcc/testsuite/gcc.target/arm/simd/vexts64.c new file mode 100644 index 0000000..7bb2012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts64.c @@ -0,0 +1,12 @@ +/* Test the `vexts64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s64.x" + +/* Don't scan assembler for vext - it can be optimized into a move from r0. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8.c b/gcc/testsuite/gcc.target/arm/simd/vexts8.c new file mode 100644 index 0000000..194e198 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts8.c @@ -0,0 +1,12 @@ +/* Test the `vexts8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16.c b/gcc/testsuite/gcc.target/arm/simd/vextu16.c new file mode 100644 index 0000000..f69c2bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu16.c @@ -0,0 +1,12 @@ +/* Test the `vextu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32.c b/gcc/testsuite/gcc.target/arm/simd/vextu32.c new file mode 100644 index 0000000..b76e383 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu32.c @@ -0,0 +1,12 @@ +/* Test the `vextu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64.c b/gcc/testsuite/gcc.target/arm/simd/vextu64.c new file mode 100644 index 0000000..39ffc56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu64.c @@ -0,0 +1,12 @@ +/* Test the `vextu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u64.x" + +/* Don't scan assembler for vext - it can be optimized into a move from r0. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8.c b/gcc/testsuite/gcc.target/arm/simd/vextu8.c new file mode 100644 index 0000000..a9d62b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu8.c @@ -0,0 +1,12 @@ +/* Test the `vextu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */