From patchwork Wed Apr 16 20:51:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pat Haugen X-Patchwork-Id: 339712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1649D1400A8 for ; Thu, 17 Apr 2014 06:52:06 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=kgexnyD9n8XmImJ2p ge3Mnsv0SNUbyjeTqre7Q/fLEwU+Ze0H8TgOIuh+/UMZFInZ7dwkBJWt8z7nGAZP 5stby/9OcSo2HN1iE9H6zwV1CUtXSoyNyQ/6bCCfcTTYFoIiLLDZnFwgbOySOcoQ U2xioB3XQjQ2ITAqPicmhnujeE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=kM+r4TwuFvtcwHVCl6bFFku 1O7A=; b=vfTNlDvNiXmXekoiBtKhXk4RDfrDxE/4DZ+kT9swyhy/A4HmntknL0A ZOUAjMXJGjxzCzvungGRLg/z1IFm909N6SxetPThkyJi8OzUDdefUfNBuRWMjans F9OCBywCjZhHZZbQZ76DkFBD4/XFY3uYHsFcErnJroqJWSy5OpJY= Received: (qmail 30029 invoked by alias); 16 Apr 2014 20:51:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30017 invoked by uid 89); 16 Apr 2014 20:51:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e7.ny.us.ibm.com Received: from e7.ny.us.ibm.com (HELO e7.ny.us.ibm.com) (32.97.182.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 16 Apr 2014 20:51:57 +0000 Received: from /spool/local by e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 16 Apr 2014 16:51:52 -0400 Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 19EE0C9001A for ; Wed, 16 Apr 2014 16:51:48 -0400 (EDT) Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by b01cxnp23033.gho.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s3GKpqFF6881562 for ; Wed, 16 Apr 2014 20:51:52 GMT Received: from d01av02.pok.ibm.com (localhost [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s3GKppSX012822 for ; Wed, 16 Apr 2014 16:51:52 -0400 Received: from pthw510.ibm.com (pthw510.ibm.com.rchland.ibm.com [9.10.86.149]) by d01av02.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s3GKpoDg012775; Wed, 16 Apr 2014 16:51:50 -0400 Message-ID: <534EED66.1080303@linux.vnet.ibm.com> Date: Wed, 16 Apr 2014 15:51:50 -0500 From: Pat Haugen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: segher@kernel.crashing.org CC: GCC Patches , David Edelsohn Subject: Re: [PATCH, rs6000] Improve TImode add/sub References: <53448F22.6000309@linux.vnet.ibm.com> <20140409025635.GA22176@gate.crashing.org> In-Reply-To: <20140409025635.GA22176@gate.crashing.org> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14041620-5806-0000-0000-000024A709B9 X-IsSubscribed: yes On 04/08/2014 09:56 PM, segher@kernel.crashing.org wrote: > +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ > +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ > Please leave out the default arguments. Why does this need skipping > on Darwin? > >> +;; Define the TImode operations that can be done in a small number >> +;; of instructions. The & constraints are to prevent the register >> +;; allocator from allocating registers that overlap with the inputs >> +;; (for example, having an input in 7,8 and an output in 6,7). We >> +;; also allow for the output being the same as one of the inputs. >> + >> +(define_insn "addti3" >> + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") >> + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") >> + (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] >> + "TARGET_POWERPC64" > That's not the correct condition: the carry bit is set based on the 32-bit > carry in 32-bit mode, so the condition has to be TARGET_64BIT. > > The adddi3 pattern has !TARGET_POWERPC64 since a 64-bit addition can > be done without addc on a 64-bit machine, no matter what mode the CPU > is in. > >> + "* >> +{ > Might as well leave out this stuff on new code, just use the braces :-) > > Updated patch with above comments incorporated. Bootstrap/regtest on BE/LE with no new regressions. Ok for trunk? -Pat Index: gcc/testsuite/gcc.target/powerpc/ti_math1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/ti_math1.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/ti_math1.c (revision 0) @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addc" 1 } } */ +/* { dg-final { scan-assembler-times "adde" 1 } } */ +/* { dg-final { scan-assembler-times "subfc" 1 } } */ +/* { dg-final { scan-assembler-times "subfe" 1 } } */ +/* { dg-final { scan-assembler-not "subf " } } */ + +__int128 +add_128 (__int128 *ptr, __int128 val) +{ + return (*ptr + val); +} + +__int128 +sub_128 (__int128 *ptr, __int128 val) +{ + return (*ptr - val); +} + Index: gcc/testsuite/gcc.target/powerpc/ti_math2.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/ti_math2.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/ti_math2.c (revision 0) @@ -0,0 +1,73 @@ +/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2 -fno-inline" } */ + +union U { + __int128 i128; + struct { + long l1; + long l2; + } s; +}; + +union U u1,u2; + +__int128 +create_128 (long most_sig, long least_sig) +{ + union U u; + +#if __LITTLE_ENDIAN__ + u.s.l1 = least_sig; + u.s.l2 = most_sig; +#else + u.s.l1 = most_sig; + u.s.l2 = least_sig; +#endif + return u.i128; +} + +long most_sig (union U * u) +{ +#if __LITTLE_ENDIAN__ + return (*u).s.l2; +#else + return (*u).s.l1; +#endif +} + +long least_sig (union U * u) +{ +#if __LITTLE_ENDIAN__ + return (*u).s.l1; +#else + return (*u).s.l2; +#endif +} + +__int128 +add_128 (__int128 *ptr, __int128 val) +{ + return (*ptr + val); +} + +__int128 +sub_128 (__int128 *ptr, __int128 val) +{ + return (*ptr - val); +} + +int +main (void) +{ + /* Do a simple add/sub to make sure carry is happening between the dwords + and that dwords are in correct endian order. */ + u1.i128 = create_128 (1, -1); + u2.i128 = add_128 (&u1.i128, 1); + if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0)) + __builtin_abort (); + u2.i128 = sub_128 (&u2.i128, 1); + if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1)) + __builtin_abort (); + return 0; +} + Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 209226) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -6535,6 +6535,49 @@ (define_insn_and_split "*floatunsdisf2_m [(set_attr "length" "8") (set_attr "type" "fpload")]) +;; Define the TImode operations that can be done in a small number +;; of instructions. The & constraints are to prevent the register +;; allocator from allocating registers that overlap with the inputs +;; (for example, having an input in 7,8 and an output in 6,7). We +;; also allow for the output being the same as one of the inputs. + +(define_insn "addti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") + (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] + "TARGET_64BIT" +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[2])) != CONST_INT + ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" + : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; + else + return (GET_CODE (operands[2])) != CONST_INT + ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" + : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + +(define_insn "subti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r") + (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I") + (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))] + "TARGET_64BIT" +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[1]) != CONST_INT) + ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" + : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; + else + return (GET_CODE (operands[1]) != CONST_INT) + ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" + : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + + ;; Define the DImode operations that can be done in a small number ;; of instructions. The & constraints are to prevent the register ;; allocator from allocating registers that overlap with the inputs