From patchwork Thu Apr 10 08:42:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 338057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C2978140084 for ; Thu, 10 Apr 2014 18:43:01 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=H/eVNJo8NeKUf4QhY6wUoR8CmfxH5mzDSFS2+FQpwLNrJl td16nF2CYq1/ET/GhCZ/OeM081SpDrusjmMGqtE0WvQdvSxudW1WI8qs/l59h7Iz 7J4n5JZstQOmGOq1tmUxpSYwijfJfnQjf4Efy4qhhhCGpliYHsHCJqUmsrAnM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=W2S7G770eW3ahVC99AN0ytEZGVw=; b=mfnwCB1PfRwjbQ7OJ00v HIMrfx7j3uQDHz9lCBB0wVLGSsLQuLZOC06Dj1jydwhAISC5L5o9JPbjIfRaCkWu 5a0xiogoZPg99kH9OLNp+HwIaKkAyv56R8xKBTU78M5DZUSLhpCLnyY0y3YjTRnS MMpKeN5G8Y4Ms01g4ftPqEc= Received: (qmail 14046 invoked by alias); 10 Apr 2014 08:42:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13971 invoked by uid 89); 10 Apr 2014 08:42:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Apr 2014 08:42:41 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 10 Apr 2014 09:42:38 +0100 Received: from [10.1.209.147] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 10 Apr 2014 09:42:50 +0100 Message-ID: <5346597B.1020108@arm.com> Date: Thu, 10 Apr 2014 09:42:35 +0100 From: Ramana Radhakrishnan User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:14.0) Gecko/20120713 Thunderbird/14.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org ;" Subject: [PATCH wwwdocs] Changes for ARM / AArch64 backends 4.9 X-MC-Unique: 114041009423800701 X-IsSubscribed: yes 4.9 changes for ARM / AArch64. Sorry it's taken me a while to get this out but better late than never :) Ok ? Ramana Index: htdocs/gcc-4.9/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.9/changes.html,v retrieving revision 1.64 diff -a -u -r1.64 changes.html --- htdocs/gcc-4.9/changes.html 22 Mar 2014 14:20:02 -0000 1.64 +++ htdocs/gcc-4.9/changes.html 9 Apr 2014 15:00:01 -0000 @@ -437,6 +437,96 @@

New Targets and Target Specific Improvements

+

AArch64

+
    +
  • The ARMv8-A crypto and CRC instructions are now supported through + intrinsics. These are enabled when the architecture supports these + and are available through the -march=armv8-a+crc + and -march=armv8-a+crypto options. +
    • +
  • Initial support for ILP32 has now been added to the + compiler. This is now available through the command line option + -mabi=ilp32. Support for ILP32 is + considered experimental as the ABI specification is still beta. +
    • +
  • Coverage of more of the ISA including the SIMD extensions has + been added. The Advanced SIMD intrinsics have also been improved. +
    • +
  • The new local register allocator (LRA) is now on by default + for the AArch64 backend. +
    • +
  • The REE (Redundant extension elimination) pass has now been enabled + by default for the AArch64 backend. +
    • +
  • Tuning for the Cortex-A53 and Cortex-A57 has been improved. +
    • +
  • Initial big.LITTLE tuning support for the combination of Cortex-A57 + and Cortex-A53 was added through the -mcpu=cortex-a57.cortex-a53 + option. +
    • +
  • A number of structural changes have been made to both the ARM + and AArch64 backends to facilitate improved code-generation. +
    • +
+ +

ARM

+
    +
  • Use of Advanced SIMD (Neon) for 64-bit scalar computations has been + disabled by default. This was found to generate better code in only + a small number of cases. It can be turned back on with the + -mneon-for-64bits option. +
    • +
  • Further support for the ARMv8-A architecture, notably implementing + the restriction around IT blocks in the Thumb32 instruction set has + been added. The -mrestrict-it option can be used with + -march=armv7-a or the -march=armv7ve options + to make code generation fully compatible with the deprecated instructions + in ARMv8-A. +
    • +
  • Support has now been added for the ARMv7ve variant of the + architecture. This can be used by the -march=armv7ve option. +
    • +
  • The ARMv8-A crypto and CRC instructions are now supported through + intrinsics and are available through the -march=armv8-a+crc + and mfpu=crypto-neon-fp-armv8 options. +
    • +
  • LRA is now on by default for the ARM target. This can be turned off + using the -mno-lra option. This option is purely + transitionary command line option and will be removed in a future + release. We are interested in any bug reports regarding functional and + performance regressions with LRA. +
    • +
  • A new option -mslow-flash-data to improve performance + of programs fetching data on slow flash memory has now been + introduced for the ARMv7-M profile cores. +
    • +
  • A new option -mpic-data-is-text-relative for targets + that allows data segments to be relative to text segments has + been added. This is on by default for all targets except VxWorks RTP. +
    • +
  • A number of infrastructural changes have been made to both the ARM + and AArch64 backends to facilitate improved code-generation. +
    • +
  • GCC now supports Cortex-A12 and the Cortex-R7 through the + -mcpu=cortex-a12 and -mcpu=cortex-r7 options. +
    • +
  • GCC now has tuning for the Cortex-A57 and Cortex-A53 + through the -mcpu=cortex-a57 and -mcpu=cortex-a53 + options. +
    • +
  • Initial big.LITTLE tuning support for the combination of Cortex-A57 + and Cortex-A53 was added through the -mcpu=cortex-a57.cortex-a53 + option. Similar support was added for the combination of + Cortex-A15 and Cortex-A7 through the -mcpu=cortex-a15.cortex-a7 + option. +
    • +
  • Further performance optimizations for the Cortex-A15 and the + Cortex-M4 have been added. +
    • +
  • A number of code generation improvements for Thumb2 to reduce code + size when compiling for the M-profile processors. +
    • +

IA-32/x86-64

  • Intel AVX-512 support was added to GCC. That includes inline