From patchwork Tue Apr 8 18:39:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pat Haugen X-Patchwork-Id: 337717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5920A1400AA for ; Wed, 9 Apr 2014 04:39:57 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=RpV9+EhQhUHwYwmDb wkswDAKzfyPbJ4o1BB73jMX29wdW8XJGLP+nuwJBghpT+0K4p+riiVJH9HpqMq+8 Amr6hh68VL7WTS8ZBOeEXhT8EA0Ml5N98/bHQTdQLsK8KvJGNOUNGZJvTH3B91en CmcQJWM/fz2zEN/XZiXnOEz+ME= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=R9E4Thu+xMiAbqfh3QE/yFs l+C0=; b=kn/qoKfyr5SCKFBV2MxfN3OBYXy39vmpxrkInAegj4OtGtCrDetcRih Yu+T8M1vPXjzuBfxlza47XvD/S2A+KM4VZq99cNSq0XPmMbiAhK93LTxUDCk68X5 emiA2gCppsM6LPwVO/q3iWJjnppUnC0PXBIYrHC5ZQ/b1HMb6lkg= Received: (qmail 8535 invoked by alias); 8 Apr 2014 18:39:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8514 invoked by uid 89); 8 Apr 2014 18:39:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e8.ny.us.ibm.com Received: from e8.ny.us.ibm.com (HELO e8.ny.us.ibm.com) (32.97.182.138) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 08 Apr 2014 18:39:47 +0000 Received: from /spool/local by e8.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 8 Apr 2014 14:39:42 -0400 Received: from b01cxnp23034.gho.pok.ibm.com (b01cxnp23034.gho.pok.ibm.com [9.57.198.29]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id 697F138C8045 for ; Tue, 8 Apr 2014 14:39:42 -0400 (EDT) Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by b01cxnp23034.gho.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s38IdgV08913220 for ; Tue, 8 Apr 2014 18:39:42 GMT Received: from d01av02.pok.ibm.com (localhost [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s38IdgXL016479 for ; Tue, 8 Apr 2014 14:39:42 -0400 Received: from pthw510.ibm.com (dyn9050022231.mts.ibm.com [9.50.22.231] (may be forged)) by d01av02.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s38Idf8I016383; Tue, 8 Apr 2014 14:39:41 -0400 Message-ID: <5344426C.9080207@linux.vnet.ibm.com> Date: Tue, 08 Apr 2014 13:39:40 -0500 From: Pat Haugen User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: GCC Patches CC: David Edelsohn Subject: Re: [PATCH, rs6000] Improve atomic_load/store code gen for Power8 TI mode References: <5331ACD0.7030004@linux.vnet.ibm.com> In-Reply-To: <5331ACD0.7030004@linux.vnet.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14040818-0320-0000-0000-000002EF5B9F X-IsSubscribed: yes On 03/25/2014 11:20 AM, Pat Haugen wrote: > Power8 can use lq/stq instructions for TI mode atomic_load/store. > Bootstrap/regtest with no new failures. Ok for trunk and 4.8 (once > bootstrap/regtest finishes)? > > -Pat > > > 2014-03-25 Pat Haugen > > * config/rs6000/sync.md (AINT mode_iterator): Move definition. > (loadsync_): Change mode. > (atomic_load, atomic_store): Add support for TI mode. > (load_quadpti, store_quadpti): New. > * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. > > gcc/testsuite: > * gcc.target/powerpc/atomic_load_store-p8.c: New. Updated patch which was approved off list and I have committed. Index: testsuite/gcc.target/powerpc/atomic_load_store-p8.c =================================================================== --- testsuite/gcc.target/powerpc/atomic_load_store-p8.c (revision 0) +++ testsuite/gcc.target/powerpc/atomic_load_store-p8.c (revision 0) @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler-times "lq" 1 } } */ +/* { dg-final { scan-assembler-times "stq" 1 } } */ +/* { dg-final { scan-assembler-not "bl __atomic" } } */ +/* { dg-final { scan-assembler-not "lqarx" } } */ +/* { dg-final { scan-assembler-not "stqcx" } } */ + +__int128 +atomic_load_128_relaxed (__int128 *ptr) +{ + return __atomic_load_n (ptr, __ATOMIC_RELAXED); +} + +void +atomic_store_128_relaxed (__int128 *ptr, __int128 val) +{ + __atomic_store_n (ptr, val, __ATOMIC_RELAXED); +} + Index: config/rs6000/predicates.md =================================================================== --- config/rs6000/predicates.md (revision 209198) +++ config/rs6000/predicates.md (working copy) @@ -624,14 +624,14 @@ (define_predicate "offsettable_mem_opera (match_test "offsettable_nonstrict_memref_p (op)"))) ;; Return 1 if the operand is suitable for load/store quad memory. -;; This predicate only checks for non-atomic loads/stores. +;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). (define_predicate "quad_memory_operand" (match_code "mem") { rtx addr, op0, op1; int ret; - if (!TARGET_QUAD_MEMORY) + if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) ret = 0; else if (!memory_operand (op, mode)) Index: config/rs6000/sync.md =================================================================== --- config/rs6000/sync.md (revision 209198) +++ config/rs6000/sync.md (working copy) @@ -107,10 +107,17 @@ (define_insn "isync" "isync" [(set_attr "type" "isync")]) +;; Types that we should provide atomic instructions for. +(define_mode_iterator AINT [QI + HI + SI + (DI "TARGET_POWERPC64") + (TI "TARGET_SYNC_TI")]) + ;; The control dependency used for load dependency described ;; in B.2.3 of the Power ISA 2.06B. (define_insn "loadsync_" - [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")] + [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")] UNSPECV_ISYNC) (clobber (match_scratch:CC 1 "=y"))] "" @@ -118,18 +125,56 @@ (define_insn "loadsync_" [(set_attr "type" "isync") (set_attr "length" "12")]) +(define_insn "load_quadpti" + [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") + (unspec:PTI + [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))] + "TARGET_SYNC_TI + && !reg_mentioned_p (operands[0], operands[1])" + "lq %0,%1" + [(set_attr "type" "load") + (set_attr "length" "4")]) + (define_expand "atomic_load" - [(set (match_operand:INT1 0 "register_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "")) ;; memory + [(set (match_operand:AINT 0 "register_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "")) ;; memory (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { + if (mode == TImode && !TARGET_SYNC_TI) + FAIL; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); if (model == MEMMODEL_SEQ_CST) emit_insn (gen_hwsync ()); - emit_move_insn (operands[0], operands[1]); + if (mode != TImode) + emit_move_insn (operands[0], operands[1]); + else + { + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti_reg = gen_reg_rtx (PTImode); + + // Can't have indexed address for 'lq' + if (indexed_address (XEXP (op1, 0), TImode)) + { + rtx old_addr = XEXP (op1, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[1] = op1 = replace_equiv_address (op1, new_addr); + } + + emit_insn (gen_load_quadpti (pti_reg, op1)); + + if (WORDS_BIG_ENDIAN) + emit_move_insn (op0, gen_lowpart (TImode, pti_reg)); + else + { + emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg)); + emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg)); + } + } switch (model) { @@ -146,12 +191,24 @@ (define_expand "atomic_load" DONE; }) +(define_insn "store_quadpti" + [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ") + (unspec:PTI + [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] + "TARGET_SYNC_TI" + "stq %1,%0" + [(set_attr "type" "store") + (set_attr "length" "4")]) + (define_expand "atomic_store" - [(set (match_operand:INT1 0 "memory_operand" "") ;; memory - (match_operand:INT1 1 "register_operand" "")) ;; input + [(set (match_operand:AINT 0 "memory_operand" "") ;; memory + (match_operand:AINT 1 "register_operand" "")) ;; input (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { + if (mode == TImode && !TARGET_SYNC_TI) + FAIL; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); switch (model) { @@ -166,7 +223,33 @@ (define_expand "atomic_store" default: gcc_unreachable (); } - emit_move_insn (operands[0], operands[1]); + if (mode != TImode) + emit_move_insn (operands[0], operands[1]); + else + { + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti_reg = gen_reg_rtx (PTImode); + + // Can't have indexed address for 'stq' + if (indexed_address (XEXP (op0, 0), TImode)) + { + rtx old_addr = XEXP (op0, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[0] = op0 = replace_equiv_address (op0, new_addr); + } + + if (WORDS_BIG_ENDIAN) + emit_move_insn (pti_reg, gen_lowpart (PTImode, op1)); + else + { + emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1)); + emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1)); + } + + emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg)); + } + DONE; }) @@ -180,14 +263,6 @@ (define_mode_iterator ATOMIC [(QI "TARGE SI (DI "TARGET_POWERPC64")]) -;; Types that we should provide atomic instructions for. - -(define_mode_iterator AINT [QI - HI - SI - (DI "TARGET_POWERPC64") - (TI "TARGET_SYNC_TI")]) - (define_insn "load_locked" [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r") (unspec_volatile:ATOMIC Index: config/rs6000/rs6000.md =================================================================== --- config/rs6000/rs6000.md (revision 209198) +++ config/rs6000/rs6000.md (working copy) @@ -125,6 +125,7 @@ (define_c_enum "unspec" UNSPEC_P8V_MTVSRD UNSPEC_P8V_XXPERMDI UNSPEC_P8V_RELOAD_FROM_VSX + UNSPEC_LSQ ]) ;;