diff mbox

aarch64 suuport for libitm

Message ID 533B3CA6.90305@redhat.com
State New
Headers show

Commit Message

Richard Henderson April 1, 2014, 10:24 p.m. UTC
Comments?  If approved, should this go in for 4.9, or wait for stage1?
Certainly it's self-contained...


r~
* configure.tgt: Handle aarch64 as target.
	* config/aarch64/sjlj.S: New file.
	* config/aarch64/target.h: New file.

Comments

Andrew Pinski April 1, 2014, 10:41 p.m. UTC | #1
On Tue, Apr 1, 2014 at 3:24 PM, Richard Henderson <rth@redhat.com> wrote:
> Comments?  If approved, should this go in for 4.9, or wait for stage1?
> Certainly it's self-contained...

On Cavium's thunder processor the cache line size is going to be
bigger than 64 bytes, what is your solution to improve performance on
target's like Thunder?

Also I think the default page size for most Linux distros is going to
be 64k on aarch64 including Redhat Linux so it makes sense not to
define FIXED_PAGE_SIZE.

I will implement the ILP32 version of this patch once it goes in,
there needs a few changes in gtm_jmpbuf due to long and pointers being
32bit but the assembly storing 64bits always.

Thanks,
Andrew


>
>
> r~
Richard Henderson April 2, 2014, 2:37 p.m. UTC | #2
On 04/01/2014 03:41 PM, Andrew Pinski wrote:
> On Tue, Apr 1, 2014 at 3:24 PM, Richard Henderson <rth@redhat.com> wrote:
>> Comments?  If approved, should this go in for 4.9, or wait for stage1?
>> Certainly it's self-contained...
> 
> On Cavium's thunder processor the cache line size is going to be
> bigger than 64 bytes, what is your solution to improve performance on
> target's like Thunder?

We can expand the number reasonably.  The only thing it controls is layout of
some of the internal data structures to attempt to put different locks on
different lines.

Is 128 big enough for Thunder?  Honestly, I may well not even have it right for
the processor we have in house.  I didn't bother trying to track down docs to
find out.

> Also I think the default page size for most Linux distros is going to
> be 64k on aarch64 including Redhat Linux so it makes sense not to
> define FIXED_PAGE_SIZE.

Heh.  It turns out these page size defines aren't used any more at all.  During
one of the rewrites we must have delete the bits that used it.  I'll get rid of
all of them so as to be less confusing.

> I will implement the ILP32 version of this patch once it goes in,
> there needs a few changes in gtm_jmpbuf due to long and pointers being
> 32bit but the assembly storing 64bits always.

I can minimize those changes now by using unsigned long long...


r~
Andrew Pinski April 2, 2014, 3:55 p.m. UTC | #3
> On Apr 2, 2014, at 7:37 AM, Richard Henderson <rth@redhat.com> wrote:
> 
>> On 04/01/2014 03:41 PM, Andrew Pinski wrote:
>>> On Tue, Apr 1, 2014 at 3:24 PM, Richard Henderson <rth@redhat.com> wrote:
>>> Comments?  If approved, should this go in for 4.9, or wait for stage1?
>>> Certainly it's self-contained...
>> 
>> On Cavium's thunder processor the cache line size is going to be
>> bigger than 64 bytes, what is your solution to improve performance on
>> target's like Thunder?
> 
> We can expand the number reasonably.  The only thing it controls is layout of
> some of the internal data structures to attempt to put different locks on
> different lines.
> 
> Is 128 big enough for Thunder?  Honestly, I may well not even have it right for
> the processor we have in house.  I didn't bother trying to track down docs to
> find out.

Yes 128 should be enough. 

Thanks,
Andrew

> 
>> Also I think the default page size for most Linux distros is going to
>> be 64k on aarch64 including Redhat Linux so it makes sense not to
>> define FIXED_PAGE_SIZE.
> 
> Heh.  It turns out these page size defines aren't used any more at all.  During
> one of the rewrites we must have delete the bits that used it.  I'll get rid of
> all of them so as to be less confusing.
> 
>> I will implement the ILP32 version of this patch once it goes in,
>> there needs a few changes in gtm_jmpbuf due to long and pointers being
>> 32bit but the assembly storing 64bits always.
> 
> I can minimize those changes now by using unsigned long long...
> 
> 
> r~
>
Marcus Shawcroft May 19, 2014, 12:15 p.m. UTC | #4
On 1 April 2014 23:24, Richard Henderson <rth@redhat.com> wrote:
> Comments?  If approved, should this go in for 4.9, or wait for stage1?
> Certainly it's self-contained...


Hi, I think this should go in, with the cache line increased to 128 as
discussed with Andrew.

/Marcus
diff mbox

Patch

diff --git a/libitm/config/aarch64/sjlj.S b/libitm/config/aarch64/sjlj.S
new file mode 100644
index 0000000..4a5e758
--- /dev/null
+++ b/libitm/config/aarch64/sjlj.S
@@ -0,0 +1,90 @@ 
+/* Copyright (C) 2014 Free Software Foundation, Inc.
+   Contributed by Richard Henderson <rth@redhat.com>.
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "asmcfi.h"
+
+	.text
+	.align	2
+	.global	_ITM_beginTransaction
+	.type	_ITM_beginTransaction, %function
+
+_ITM_beginTransaction:
+	cfi_startproc
+	mov	x1, sp
+	stp	x29, x30, [sp, -11*16]!
+	cfi_adjust_cfa_offset(11*16)
+	cfi_rel_offset(x30, 8)
+	stp	x19, x20, [sp, 1*16]
+	stp	x21, x22, [sp, 2*16]
+	stp	x23, x24, [sp, 3*16]
+	stp	x25, x26, [sp, 4*16]
+	stp	x27, x28, [sp, 5*16]
+	stp	d8, d9,   [sp, 6*16]
+	stp	d10, d11, [sp, 7*16]
+	stp	d12, d13, [sp, 8*16]
+	stp	d14, d15, [sp, 9*16]
+	str	x1, [sp, 10*16]
+
+	/* Invoke GTM_begin_transaction with the struct we just built.  */
+	mov	x1, sp
+	bl	GTM_begin_transaction
+
+	/* Return; we don't need to restore any of the call-saved regs.  */
+	ldr	x30, [sp, 8]
+	add     sp, sp, #11*16
+	cfi_adjust_cfa_offset(-11*16)
+	cfi_restore(x30)
+	ret
+	cfi_endproc
+	.size	_ITM_beginTransaction, . - _ITM_beginTransaction
+
+	.align	2
+	.global	GTM_longjmp
+	.hidden	GTM_longjmp
+	.type	GTM_longjmp, %function
+
+GTM_longjmp:
+	/* The first parameter becomes the return value (x0).
+	   The third parameter is ignored for now.  */
+	cfi_startproc
+	ldp	x19, x20, [x1, 1*16]
+	ldp	x21, x22, [x1, 2*16]
+	ldp	x23, x24, [x1, 3*16]
+	ldp	x25, x26, [x1, 4*16]
+	ldp	x27, x28, [x1, 5*16]
+	ldp	d8, d9,   [x1, 6*16]
+	ldp	d10, d11, [x1, 7*16]
+	ldp	d12, d13, [x1, 8*16]
+	ldp	d14, d15, [x1, 9*16]
+	ldr	x3, [x1, 10*16]
+	ldp	x29, x30, [x1]
+	cfi_def_cfa(x1, 0)
+	mov	sp, x3
+	br	x30
+	cfi_endproc
+	.size	GTM_longjmp, . - GTM_longjmp
+
+#ifdef __linux__
+.section .note.GNU-stack, "", %progbits
+#endif
diff --git a/libitm/config/aarch64/target.h b/libitm/config/aarch64/target.h
new file mode 100644
index 0000000..efd26ab
--- /dev/null
+++ b/libitm/config/aarch64/target.h
@@ -0,0 +1,49 @@ 
+/* Copyright (C) 2014 Free Software Foundation, Inc.
+   Contributed by Richard Henderson <rth@redhat.com>.
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+namespace GTM HIDDEN {
+
+typedef struct gtm_jmpbuf
+{
+  unsigned long fp;		/* x29 */
+  unsigned long pc;		/* x30 */
+  unsigned long gr[10];		/* x19-x28 */
+  unsigned long vr[8];		/* d8-d15 */
+  void *cfa;
+} gtm_jmpbuf;
+
+/* ??? AArch64 can use either 4k or 64k pages.  */
+#define PAGE_SIZE	4096
+#define FIXED_PAGE_SIZE	1
+
+/* ??? The size of one line in hardware caches (in bytes). */
+#define HW_CACHELINE_SIZE 64
+
+static inline void
+cpu_relax (void)
+{
+  __asm volatile ("" : : : "memory");
+}
+
+} // namespace GTM
diff --git a/libitm/configure.tgt b/libitm/configure.tgt
index 4694a9b..44c1a14 100644
--- a/libitm/configure.tgt
+++ b/libitm/configure.tgt
@@ -46,6 +46,7 @@  fi
 # Map the target cpu to an ARCH sub-directory.  At the same time,
 # work out any special compilation flags as necessary.
 case "${target_cpu}" in
+  aarch64*)		ARCH=aarch64 ;;
   alpha*)		ARCH=alpha ;;
   rs6000 | powerpc*)
 	XCFLAGS="${XCFLAGS} -mhtm"