From patchwork Sat Mar 15 03:36:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 330607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 660922C009C for ; Sat, 15 Mar 2014 14:37:01 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=uAfhWgGD+1uq60h0SRzSsjvA5UWbgIpfImQR+KdBz6kGWI bAUQRjSMXlsAE7watXx9RKXLeLnQ3ITNhCQXFBS/sHj4A712ma8NBvBRw/lJ6Gss T2pw7QFFh+NthtK57RQWo25FM2OnXXIN9xx+nUNwk7hjGlLTtP0I/6F16bt7Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=a9EPo5SG+4rmzY8y/j5MkniVqHg=; b=tmM+mKzH6wbzj1e6Xdg2 nbXxHJxxXRE7miigj6XgyPAwUigXl8qHEyLuvxKGaMbDaWNeUXTh4j7YQiFWuYn/ jLVXmOTAHo5a5YZZCFP3shM6LVknMuqBuIGyOdaEVXkDoJBlapRaO720IaWhRYO2 t4OTAOAVd9dNjlqkADkBLzs= Received: (qmail 17613 invoked by alias); 15 Mar 2014 03:36:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17600 invoked by uid 89); 15 Mar 2014 03:36:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.1 required=5.0 tests=AWL, BAYES_00, SPF_HELO_PASS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 15 Mar 2014 03:36:50 +0000 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s2F3anYE007431 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 14 Mar 2014 23:36:49 -0400 Received: from pike.twiddle.home (vpn-51-208.rdu2.redhat.com [10.10.51.208]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s2F3alMU001750 for ; Fri, 14 Mar 2014 23:36:47 -0400 Message-ID: <5323CACD.4060903@redhat.com> Date: Fri, 14 Mar 2014 20:36:45 -0700 From: Richard Henderson User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: GCC Patches Subject: [COMMITTED] Fix target/60525 -- i386 float ICEs X-IsSubscribed: yes This PR is fallout from my patch from yesterday, which adjusted some of the i386 float->int conversion patterns. In the gcc-patches message for that change, I opined that in stage1 we should clean up all of these patterns. Except that the existing state of affairs appears to have been too complex for me to make small changes and get all of the fiddly bits right. Cleaning all of this up now turns out to be the best way for me to ensure that all of the patterns are in sync. The diffstat of the two patches is impressive: > i386-protos.h | 4 > i386.c | 105 -------- > i386.md | 761 +++++++++------------------------------------------------- > 3 files changed, 133 insertions(+), 737 deletions(-) over 600 lines removed from these conversion patterns. Anyway, tested by me with -march=generic, and by the reporter with -march=amdfam10. r~ PR target/60525 * config/i386/i386.md (floathi2): Delete expander; rename define_insn from *floathi2_i387; allow nonimmediate_operand. (*floathi2_i387_with_temp): Remove. (floathi splitters): Remove. (floatxf2): New pattern. (float2): Rename from float2. Drop code that tried to handle DImode for 32-bit, but which was excluded by the pattern's condition. Drop allocation of stack temporary. (*floatsi2_vector_mixed_with_temp): Remove. (*float2_mixed_with_temp): Remove. (*float2_mixed_interunit): Remove. (*float2_mixed_nointerunit): Remove. (*floatsi2_vector_sse_with_temp): Remove. (*float2_sse_with_temp): Remove. (*float2_sse_interunit): Remove. (*float2_sse_nointerunit): Remove. (*float2_i387_with_temp): Remove. (*float2_i387): Remove. (all float _with_temp splitters): Remove. (*float2_i387): New pattern. (*float2_sse): New pattern. (float TARGET_USE_VECTOR_CONVERTS splitters): Merge them. (float TARGET_SSE_PARTIAL_REG_DEPENDENCY splitters): Merge them. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 03939fd..a824e78 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4653,36 +4653,12 @@ ;; Conversion between fixed point and floating point. ;; Even though we only accept memory inputs, the backend _really_ -;; wants to be able to do this between registers. +;; wants to be able to do this between registers. Thankfully, LRA +;; will fix this up for us during register allocation. -(define_expand "floathi2" - [(parallel [(set (match_operand:X87MODEF 0 "register_operand") - (float:X87MODEF - (match_operand:HI 1 "nonimmediate_operand"))) - (clobber (match_dup 2))])] - "TARGET_80387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387)" -{ - operands[2] = assign_386_stack_local (HImode, SLOT_TEMP); -}) - -(define_insn "*floathi2_i387_with_temp" - [(set (match_operand:X87MODEF 0 "register_operand" "=f,f") - (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m,?r"))) - (clobber (match_operand:HI 2 "memory_operand" "=X,m"))] - "TARGET_80387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387)" - "#" - [(set_attr "type" "fmov,multi") - (set_attr "mode" "") - (set_attr "unit" "*,i387") - (set_attr "fp_int_src" "true")]) - -(define_insn "*floathi2_i387" +(define_insn "floathi2" [(set (match_operand:X87MODEF 0 "register_operand" "=f") - (float:X87MODEF (match_operand:HI 1 "memory_operand" "m")))] + (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m")))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)" @@ -4691,50 +4667,31 @@ (set_attr "mode" "") (set_attr "fp_int_src" "true")]) -(define_split - [(set (match_operand:X87MODEF 0 "register_operand") - (float:X87MODEF (match_operand:HI 1 "register_operand"))) - (clobber (match_operand:HI 2 "memory_operand"))] - "TARGET_80387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && reload_completed" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) (float:X87MODEF (match_dup 2)))]) - -(define_split - [(set (match_operand:X87MODEF 0 "register_operand") - (float:X87MODEF (match_operand:HI 1 "memory_operand"))) - (clobber (match_operand:HI 2 "memory_operand"))] - "TARGET_80387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && reload_completed" - [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]) +(define_insn "floatxf2" + [(set (match_operand:XF 0 "register_operand" "=f") + (float:XF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))] + "TARGET_80387" + "fild%Z1\t%1" + [(set_attr "type" "fmov") + (set_attr "mode" "XF") + (set_attr "fp_int_src" "true")]) -(define_expand "float2" - [(parallel [(set (match_operand:X87MODEF 0 "register_operand") - (float:X87MODEF - (match_operand:SWI48x 1 "nonimmediate_operand"))) - (clobber (match_dup 2))])] - "TARGET_80387 - || ((mode != DImode || TARGET_64BIT) - && SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" +(define_expand "float2" + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))] + "TARGET_80387 || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" { - bool native_int = TARGET_64BIT || mode != DImode; - - if (!(native_int - && SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - && !X87_ENABLE_FLOAT (mode, mode)) + if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) + && !X87_ENABLE_FLOAT (mode, mode)) { rtx reg = gen_reg_rtx (XFmode); rtx (*insn)(rtx, rtx); - emit_insn (gen_floatxf2 (reg, operands[1])); + emit_insn (gen_floatxf2 (reg, operands[1])); - if (mode == SFmode) + if (mode == SFmode) insn = gen_truncxfsf2; - else if (mode == DFmode) + else if (mode == DFmode) insn = gen_truncxfdf2; else gcc_unreachable (); @@ -4742,83 +4699,22 @@ emit_insn (insn (operands[0], reg)); DONE; } - - /* Avoid store forwarding (partial memory) stall penalty - by passing DImode value through XMM registers. */ - if (!native_int - && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC - && optimize_function_for_speed_p (cfun)) - { - operands[2] = assign_386_stack_local (mode, SLOT_TEMP); - emit_insn (gen_floatdi2_i387_with_xmm (operands[0], - operands[1], - operands[2])); - DONE; - } - - /* Notice when we'd convert directly from general registers. */ - if (native_int - && (TARGET_MIX_SSE_I387 || TARGET_SSE_MATH) - && SSE_FLOAT_MODE_P (mode) - && (TARGET_INTER_UNIT_CONVERSIONS - || optimize_function_for_size_p (cfun))) - { - emit_insn (gen_rtx_SET - (VOIDmode, operands[0], - gen_rtx_FLOAT (mode, operands[1]))); - DONE; - } - - operands[2] = assign_386_stack_local (mode, SLOT_TEMP); }) -(define_insn "*floatsi2_vector_mixed_with_temp" - [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x,x") - (float:MODEF - (match_operand:SI 1 "nonimmediate_operand" "m,?r,r,m,!x"))) - (clobber (match_operand:SI 2 "memory_operand" "=X,m,m,X,m"))] - "TARGET_SSE2 && TARGET_MIX_SSE_I387 - && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)" - "#" - [(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt") - (set_attr "mode" ",,,,") - (set_attr "unit" "*,i387,*,*,*") - (set_attr "athlon_decode" "*,*,double,direct,double") - (set_attr "amdfam10_decode" "*,*,vector,double,double") - (set_attr "bdver1_decode" "*,*,double,direct,double") - (set_attr "fp_int_src" "true")]) - -(define_insn "*float2_mixed_with_temp" - [(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x") - (float:MODEF - (match_operand:SWI48 1 "nonimmediate_operand" "m,?r,r,m"))) - (clobber (match_operand:SWI48 2 "memory_operand" "=X,m,m,X"))] - "SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387" - "#" - [(set_attr "type" "fmov,multi,sseicvt,sseicvt") +(define_insn "*float2_i387" + [(set (match_operand:MODEF 0 "register_operand" "=f") + (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "m")))] + "TARGET_80387 && !(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" + "fild%Z1\t%1" + [(set_attr "type" "fmov") (set_attr "mode" "") - (set_attr "unit" "*,i387,*,*") - (set_attr "athlon_decode" "*,*,double,direct") - (set_attr "amdfam10_decode" "*,*,vector,double") - (set_attr "bdver1_decode" "*,*,double,direct") (set_attr "fp_int_src" "true")]) -(define_split - [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SWI48 1 "register_operand"))) - (clobber (match_operand:SWI48 2 "memory_operand"))] - "SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387 - && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) - && reload_completed && SSE_REG_P (operands[0])" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) (float:MODEF (match_dup 2)))]) - -(define_insn "*float2_mixed_interunit" +(define_insn "*float2_sse" [(set (match_operand:MODEF 0 "register_operand" "=f,x,x") (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))] - "SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387 - && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" "@ fild%Z1\t%1 %vcvtsi2\t{%1, %d0|%d0, %1} @@ -4836,93 +4732,27 @@ (set_attr "athlon_decode" "*,double,direct") (set_attr "amdfam10_decode" "*,vector,double") (set_attr "bdver1_decode" "*,double,direct") - (set_attr "fp_int_src" "true")]) - -(define_insn "*float2_mixed_nointerunit" - [(set (match_operand:MODEF 0 "register_operand" "=f,x") - (float:MODEF - (match_operand:SWI48 1 "memory_operand" "m,m")))] - "SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387 - && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" - "@ - fild%Z1\t%1 - %vcvtsi2\t{%1, %d0|%d0, %1}" - [(set_attr "type" "fmov,sseicvt") - (set_attr "prefix" "orig,maybe_vex") - (set_attr "mode" "") - (set (attr "prefix_rex") - (if_then_else - (and (eq_attr "prefix" "maybe_vex") - (match_test "mode == DImode")) - (const_string "1") - (const_string "*"))) - (set_attr "athlon_decode" "*,direct") - (set_attr "amdfam10_decode" "*,double") - (set_attr "bdver1_decode" "*,direct") - (set_attr "fp_int_src" "true")]) - -(define_insn "*floatsi2_vector_sse_with_temp" - [(set (match_operand:MODEF 0 "register_operand" "=x,x,x") - (float:MODEF - (match_operand:SI 1 "nonimmediate_operand" "r,m,!x"))) - (clobber (match_operand:SI 2 "memory_operand" "=m,X,m"))] - "TARGET_SSE2 && TARGET_SSE_MATH - && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)" - "#" - [(set_attr "type" "sseicvt") - (set_attr "mode" ",,") - (set_attr "athlon_decode" "double,direct,double") - (set_attr "amdfam10_decode" "vector,double,double") - (set_attr "bdver1_decode" "double,direct,double") - (set_attr "fp_int_src" "true")]) - -(define_split - [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SI 1 "register_operand"))) - (clobber (match_operand:SI 2 "memory_operand"))] - "TARGET_SSE2 && TARGET_SSE_MATH - && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) - && reload_completed && SSE_REG_P (operands[0])" - [(const_int 0)] -{ - rtx op1 = operands[1]; - - operands[3] = simplify_gen_subreg (mode, operands[0], - mode, 0); - if (GET_CODE (op1) == SUBREG) - op1 = SUBREG_REG (op1); - - if (GENERAL_REG_P (op1) && TARGET_INTER_UNIT_MOVES_TO_VEC) - { - operands[4] = simplify_gen_subreg (V4SImode, operands[0], mode, 0); - emit_insn (gen_sse2_loadld (operands[4], - CONST0_RTX (V4SImode), operands[1])); - } - /* We can ignore possible trapping value in the - high part of SSE register for non-trapping math. */ - else if (SSE_REG_P (op1) && !flag_trapping_math) - operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0); - else - { - operands[4] = simplify_gen_subreg (V4SImode, operands[0], mode, 0); - emit_move_insn (operands[2], operands[1]); - emit_insn (gen_sse2_loadld (operands[4], - CONST0_RTX (V4SImode), operands[2])); - } - if (mode == V4SFmode) - emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); - else - emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); - DONE; -}) + (set_attr "fp_int_src" "true") + (set (attr "enabled") + (cond [(eq_attr "alternative" "0") + (symbol_ref "TARGET_MIX_SSE_I387") + (eq_attr "alternative" "1") + (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS + || optimize_function_for_size_p (cfun)") + ] + (symbol_ref "true"))) + ]) +;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory +;; slots when !TARGET_INTER_UNIT_MOVES_TO_VEC disables the general_regs +;; alternative in sse2_loadld. (define_split [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SI 1 "memory_operand"))) - (clobber (match_operand:SI 2 "memory_operand"))] + (float:MODEF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) - && reload_completed && SSE_REG_P (operands[0])" + && reload_completed && SSE_REG_P (operands[0]) + && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)" [(const_int 0)] { operands[3] = simplify_gen_subreg (mode, operands[0], @@ -4931,27 +4761,7 @@ emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), operands[1])); - if (mode == V4SFmode) - emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); - else - emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); - DONE; -}) -(define_split - [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SI 1 "memory_operand")))] - "TARGET_SSE2 && TARGET_SSE_MATH - && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) - && reload_completed && SSE_REG_P (operands[0])" - [(const_int 0)] -{ - operands[3] = simplify_gen_subreg (mode, operands[0], - mode, 0); - operands[4] = simplify_gen_subreg (V4SImode, operands[0], mode, 0); - - emit_insn (gen_sse2_loadld (operands[4], - CONST0_RTX (V4SImode), operands[1])); if (mode == V4SFmode) emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); else @@ -4959,166 +4769,27 @@ DONE; }) -(define_insn "*float2_sse_with_temp" - [(set (match_operand:MODEF 0 "register_operand" "=x,x") - (float:MODEF - (match_operand:SWI48 1 "nonimmediate_operand" "r,m"))) - (clobber (match_operand:SWI48 2 "memory_operand" "=m,X"))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" - "#" - [(set_attr "type" "sseicvt") - (set_attr "mode" "") - (set_attr "athlon_decode" "double,direct") - (set_attr "amdfam10_decode" "vector,double") - (set_attr "bdver1_decode" "double,direct") - (set_attr "btver2_decode" "double,double") - (set_attr "fp_int_src" "true")]) - -(define_insn "*float2_sse_interunit" - [(set (match_operand:MODEF 0 "register_operand" "=x,x") - (float:MODEF - (match_operand:SWI48 1 "nonimmediate_operand" "r,m")))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" - "%vcvtsi2\t{%1, %d0|%d0, %1}" - [(set_attr "type" "sseicvt") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "") - (set (attr "prefix_rex") - (if_then_else - (and (eq_attr "prefix" "maybe_vex") - (match_test "mode == DImode")) - (const_string "1") - (const_string "*"))) - (set_attr "athlon_decode" "double,direct") - (set_attr "amdfam10_decode" "vector,double") - (set_attr "bdver1_decode" "double,direct") - (set_attr "btver2_decode" "double,double") - (set_attr "fp_int_src" "true")]) - -(define_split - [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand"))) - (clobber (match_operand:SWI48 2 "memory_operand"))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) - && reload_completed && SSE_REG_P (operands[0])" - [(set (match_dup 0) (float:MODEF (match_dup 1)))]) - -(define_insn "*float2_sse_nointerunit" - [(set (match_operand:MODEF 0 "register_operand" "=x") - (float:MODEF - (match_operand:SWI48 1 "memory_operand" "m")))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))" - "%vcvtsi2\t{%1, %d0|%d0, %1}" - [(set_attr "type" "sseicvt") - (set_attr "prefix" "maybe_vex") - (set_attr "mode" "") - (set (attr "prefix_rex") - (if_then_else - (and (eq_attr "prefix" "maybe_vex") - (match_test "mode == DImode")) - (const_string "1") - (const_string "*"))) - (set_attr "athlon_decode" "direct") - (set_attr "amdfam10_decode" "double") - (set_attr "bdver1_decode" "direct") - (set_attr "fp_int_src" "true")]) - -(define_split - [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SWI48 1 "register_operand"))) - (clobber (match_operand:SWI48 2 "memory_operand"))] - "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH - && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) - && reload_completed && SSE_REG_P (operands[0])" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) (float:MODEF (match_dup 2)))]) - -(define_insn "*float2_i387_with_temp" - [(set (match_operand:X87MODEF 0 "register_operand" "=f,f") - (float:X87MODEF - (match_operand:SWI48x 1 "nonimmediate_operand" "m,?r"))) - (clobber (match_operand:SWI48x 2 "memory_operand" "=X,m"))] - "TARGET_80387 - && X87_ENABLE_FLOAT (mode, mode)" - "@ - fild%Z1\t%1 - #" - [(set_attr "type" "fmov,multi") - (set_attr "mode" "") - (set_attr "unit" "*,i387") - (set_attr "fp_int_src" "true")]) - -(define_insn "*float2_i387" - [(set (match_operand:X87MODEF 0 "register_operand" "=f") - (float:X87MODEF - (match_operand:SWI48x 1 "memory_operand" "m")))] - "TARGET_80387 - && X87_ENABLE_FLOAT (mode, mode)" - "fild%Z1\t%1" - [(set_attr "type" "fmov") - (set_attr "mode" "") - (set_attr "fp_int_src" "true")]) - -(define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand") - (float:X87MODEF (match_operand:SWI48x 1 "register_operand"))) - (clobber (match_operand:SWI48x 2 "memory_operand"))] - "TARGET_80387 - && X87_ENABLE_FLOAT (mode, mode) - && reload_completed" - [(set (match_dup 2) (match_dup 1)) - (set (match_dup 0) (float:X87MODEF (match_dup 2)))]) - -(define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand") - (float:X87MODEF (match_operand:SWI48x 1 "memory_operand"))) - (clobber (match_operand:SWI48x 2 "memory_operand"))] - "TARGET_80387 - && X87_ENABLE_FLOAT (mode, mode) - && reload_completed" - [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]) - ;; Avoid partial SSE register dependency stalls - (define_split [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:SI 1 "nonimmediate_operand")))] + (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REG_DEPENDENCY && optimize_function_for_speed_p (cfun) && reload_completed && SSE_REG_P (operands[0])" - [(set (match_dup 0) - (vec_merge: - (vec_duplicate: - (float:MODEF (match_dup 1))) - (match_dup 0) - (const_int 1)))] + [(const_int 0)] { - operands[0] = simplify_gen_subreg (mode, operands[0], - mode, 0); - emit_move_insn (operands[0], CONST0_RTX (mode)); -}) + const enum machine_mode vmode = mode; + const enum machine_mode mode = mode; + rtx t, op0 = simplify_gen_subreg (vmode, operands[0], mode, 0); -(define_split - [(set (match_operand:MODEF 0 "register_operand") - (float:MODEF (match_operand:DI 1 "nonimmediate_operand")))] - "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH - && TARGET_SSE_PARTIAL_REG_DEPENDENCY - && optimize_function_for_speed_p (cfun) - && reload_completed && SSE_REG_P (operands[0])" - [(set (match_dup 0) - (vec_merge: - (vec_duplicate: - (float:MODEF (match_dup 1))) - (match_dup 0) - (const_int 1)))] -{ - operands[0] = simplify_gen_subreg (mode, operands[0], - mode, 0); - emit_move_insn (operands[0], CONST0_RTX (mode)); + emit_move_insn (op0, CONST0_RTX (vmode)); + + t = gen_rtx_FLOAT (mode, operands[1]); + t = gen_rtx_VEC_DUPLICATE (vmode, t); + t = gen_rtx_VEC_MERGE (vmode, t, op0, const1_rtx); + emit_insn (gen_rtx_SET (VOIDmode, op0, t)); + DONE; }) ;; Break partial reg stall for cvtsd2ss.