From patchwork Tue Feb 18 14:55:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 321515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 95F232C00CA for ; Wed, 19 Feb 2014 01:59:43 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type:content-transfer-encoding; q=dns; s= default; b=ck5eYb00KFIcS0YUx7p/oUDS15iwtGwsnwhq3JmsfjI23U9jsvI/G lp6wosQYPisHixVQTfuEF2vyatmFN8Awcoo5lFTpjfPOFswQLNxZKccFJkEuTSHE GsATbJwPshtXF+G5apMonk2NhIyb5AUzc4rfdVZLARzG54QhEcPW1A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type:content-transfer-encoding; s=default; bh=fZ/X7+FeqxKmvy0p73/GZumdHhc=; b=vHNod1M3JO6V3jvgDUZUtKL+oA4F fgo/AJrQSdbn1ReL/WWPQn4pMLWSwO2o4HyP7ikFqx9Kk2GvRkfbMGX1Cjp1Aybi P0mJ6Y0gG3uNjvad2jMrnI8MOCJVYoT+LX+vOrDGEPmtSuVdcEccp0OJWeMG/FpF FqDBuDI1ohnhgAc= Received: (qmail 27295 invoked by alias); 18 Feb 2014 14:59:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 27286 invoked by uid 89); 18 Feb 2014 14:59:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.2 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Feb 2014 14:59:36 +0000 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s1IExY4D011192 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Tue, 18 Feb 2014 09:59:34 -0500 Received: from [10.36.7.35] (vpn1-7-35.ams2.redhat.com [10.36.7.35]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s1IExVBt027525 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Tue, 18 Feb 2014 09:59:32 -0500 Message-ID: <53037466.90409@redhat.com> Date: Tue, 18 Feb 2014 14:55:34 +0000 From: nick clifton User-Agent: Mozilla/5.0 (X11; Linux i686; rv:26.0) Gecko/20100101 Firefox/26.0 SeaMonkey/2.23 MIME-Version: 1.0 To: DJ Delorie CC: gcc-patches@gcc.gnu.org Subject: Re: RFA: RL78: Add missing instruction patterns References: <871tz57wfm.fsf@redhat.com> <201402141901.s1EJ1eDP007983@greed.delorie.com> In-Reply-To: <201402141901.s1EJ1eDP007983@greed.delorie.com> X-IsSubscribed: yes Hi DJ, > I'm OK with adding patterns in general, but I wonder if gcc would > produce better code if they were split into QImode ops earlier? Probably. In fact I double checked and I can no longer find the tests that triggered the need for the new "andhi3" and "xorhi3" patterns, so the revised patch below removes them, Cheers Nick gcc/ChangeLog 2014-02-18 Nick Clifton * config/rl78/rl78-real.md (cbranchsi4_real_signed): Add anti-cacnonical alternatives. (negandhi3_real): New pattern. * config/rl78/rl78-virt.md (negandhi3_virt): New pattern. Index: gcc/config/rl78/rl78-real.md =================================================================== --- gcc/config/rl78/rl78-real.md (revision 207836) +++ gcc/config/rl78/rl78-real.md (working copy) @@ -411,8 +411,8 @@ (define_insn "*cbranchsi4_real_signed" [(set (pc) (if_then_else (match_operator 0 "rl78_cmp_operator_signed" - [(match_operand:SI 1 "nonimmediate_operand" "vU,vU,vU") - (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v")]) + [(match_operand:SI 1 "general_operand" "vU,vU,vU,i,i") + (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")]) (label_ref (match_operand 3 "" "")) (pc))) (clobber (reg:HI AX_REG)) @@ -421,7 +421,9 @@ "@ movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;not1 CY\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3 movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\; movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3 - movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3" + movw ax,%H1 \;cmpw ax, %H2 \;xor1 CY,a.7\;xor1 CY,%E2.7\;movw ax,%h1 \;sknz \;cmpw ax, %h2 \;sk%C0 \;br\t!!%3 + movw ax, %H1\; cmpw ax, %H2\; xor1 CY, a.7\; not1 CY\; movw ax, %h1 \;sknz\; cmpw ax, %h2 \;sk%0 \;br\t!!%3 + movw ax, %H1\; cmpw ax, %H2\; xor1 CY, a.7\; movw ax, %h1\; sknz\; cmpw ax, %h2\; sk%0\; br\t!!%3" ) (define_insn "*cbranchsi4_real" @@ -549,3 +551,12 @@ [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))] ) +(define_insn "*negandhi3_real" + [(set (match_operand:HI 0 "register_operand" "=A") + (and:HI (neg:HI (match_operand:HI 1 "register_operand" "0")) + (match_operand:HI 2 "immediate_operand" "n"))) + ] + "rl78_real_insns_ok ()" + "xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x" +) + Index: gcc/config/rl78/rl78-virt.md =================================================================== --- gcc/config/rl78/rl78-virt.md (revision 207836) +++ gcc/config/rl78/rl78-virt.md (working copy) @@ -405,3 +405,12 @@ ] "rl78_setup_peep_movhi (operands);" ) + +(define_insn "*negandhi3_virt" + [(set (match_operand:HI 0 "register_operand" "=v") + (and:HI (neg:HI (match_operand:HI 1 "register_operand" "0")) + (match_operand:HI 2 "immediate_operand" "n"))) + ] + "rl78_virt_insns_ok ()" + "v.nand\t%0, %1, %2" +)