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[AArch64] Define vec_extract.

Message ID 5278F76F.5060104@arm.com
State New
Headers show

Commit Message

Tejas Belagod Nov. 5, 2013, 1:49 p.m. UTC 
Hi,

The attached patch defines standard pattern name vec_extract for aarch64.

Tested on aarch64-none-elf and aarch64_be-none-elf. OK for trunk?

Thanks,
Tejas Belagod
ARM.

Changelog:

2013-11-05  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (vec_extract): New.

Comments

Marcus Shawcroft Nov. 5, 2013, 6:22 p.m. UTC | #1 
On 5 November 2013 13:49, Tejas Belagod <tbelagod@arm.com> wrote:

> 2013-11-05  Tejas Belagod  <tejas.belagod@arm.com>
>
> gcc/
>         * config/aarch64/aarch64-simd.md (vec_extract): New.

OK
/Marcus
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a747ee8..879a0fd 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4578,3 +4578,19 @@ 
    (set_attr "simd_mode" "<MODE>")]
 )
 
+;; Standard pattern name vec_extract<mode>.
+
+(define_insn "vec_extract<mode>"
+  [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv")
+	(vec_select:<VEL>
+	  (match_operand:VALL 1 "register_operand" "w, w, w")
+	  (parallel [(match_operand:SI 2 "immediate_operand" "i,i,i")])))]
+  "TARGET_SIMD"
+  "@
+  umov\\t%<vw>0, %1.<Vetype>[%2]
+  dup\\t%<Vetype>0, %1.<Vetype>[%2]
+  st1\\t{%1.<Vetype>}[%2], %0"
+  [(set_attr "simd_type" "simd_movgp, simd_dup, simd_store1s")
+   (set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")
+   (set_attr "simd_mode" "<MODE>")]
+)