From patchwork Thu Oct 17 16:40:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Shawcroft X-Patchwork-Id: 284310 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 36D522C0089 for ; Fri, 18 Oct 2013 03:40:33 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=BEkmdLKlIDTBLqiIFmorWF1NUJefeMGER56WP0OEqYgNvC 50mAcE89jxbcBwAUK9lnSKWhbFZOP9yPF9ZAawHL9hKNUwubcs/6auqAs1xGjvwC XYJJ6Fu8MFuC6DF9gjgpvI97gQ3KypKVp3L3fzhethvQTM6PfIV1PpffxBtgA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=BDRSTDQpnSOyKJ3bi5+FoU49k04=; b=gQ62USmi/nQhl3Zy3kXj l1deIKG/lQGznbGUopstvJE772DxRMlAy73wuvTJ0mRacmZv+0169528iLGq5P/X y7+AEWYGEd7qeIF/kfmOqZjUYkGLjpOhB3xIRBTUKTQXVwLf9sZi8Pw8wXpsIF8f mxf32msYb2BjK+DvXVP+eFY= Received: (qmail 5207 invoked by alias); 17 Oct 2013 16:40:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5168 invoked by uid 89); 17 Oct 2013 16:40:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 Oct 2013 16:40:20 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 17 Oct 2013 17:40:17 +0100 Received: from [10.1.207.140] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Thu, 17 Oct 2013 17:39:40 +0100 Message-ID: <526012EF.5090105@arm.com> Date: Thu, 17 Oct 2013 17:40:15 +0100 From: Marcus Shawcroft User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [AArch64,PATCH] Adjust preferred_reload_class of SP+C X-MC-Unique: 113101717401703101 Hi, This patch addresses an issue in reload triggered by the gfortran.dg/loc_2.f90 regression test at -O3 with LRA disabled. The patch is based on work done by Ian Bolton here at ARM which I've dusted down and submitted. Following SFP elimination and under heavy register pressure, reload attempts the reload of SP+offset into a V register. The AArch64 instruction set does not support such an operation. We considered two solutions to this issue: 1) Detect the SP+offset pattern in secondary reload and use an intermediate X register. 2) Detect the SP+offset->V pattern in preferred_reload_class and return NO_REG before secondary reload gets involved. The latter looks like a simpler and more intuitive solution to me than the first. I also note that the i386 backend implementation of preferred_reload_class contains equivalent code. I intend to leave this patch on the list for a few days before committing to give folks knowledgable on reload and the associated target hooks the opportunity to comment. Thanks /Marcus 2013-10-17 Ian Bolton Marcus Shawcroft * config/aarch64/aarch64.c (aarch64_preferred_reload_class): Special case reload SP+C into none GENERAL_REGS. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 7fce7a0..cc9ecdd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4237,6 +4237,24 @@ aarch64_preferred_reload_class (rtx x, reg_class_t regclass) && !aarch64_simd_imm_scalar_p (x, GET_MODE (x))) return NO_REGS; + /* Register eliminiation can result in a request for + SP+constant->FP_REGS. We cannot support such operations which + use SP as source and an FP_REG as destination, so reject out + right now. */ + if (! reg_class_subset_p (regclass, GENERAL_REGS) && GET_CODE (x) == PLUS) + { + rtx lhs = XEXP (x, 0); + + /* Look through a possible SUBREG introduced by ILP32. */ + if (GET_CODE (lhs) == SUBREG) + lhs = SUBREG_REG (lhs); + + gcc_assert (REG_P (lhs)); + gcc_assert (reg_class_subset_p (REGNO_REG_CLASS (REGNO (lhs)), + POINTER_REGS)); + return NO_REGS; + } + return regclass; }