From patchwork Tue Sep 10 17:12:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yufeng Zhang X-Patchwork-Id: 273939 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A861B2C00E5 for ; Wed, 11 Sep 2013 03:12:13 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=JcqaqgNhcod4TaxTi EWruLcqqvMmuPFB11gWG/YzZA39POCMHpp/TnZA6KnpgdSO2o6EZ/xRBToVE9MqT +ZAp75wafVnsLwm7Uz/aZfmlDDSmVayfxVCsdlfXgRnLjIdHpI9J9Lzb0tTJCH40 Z2C98WXrqDobgbT9CC2Dn6F4R0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=HV1pkLt0myQgZNxefMa27jh gmk0=; b=N/vsnBbYVG0wg0CgTqBnEnJ82X1YESuVrvDCF2ilfmPXP6kA1pRyhIe ToihLnB4Kk11j48XJiIuikr/P352VeDVazymKACKVuS6y6Ni3E1jEI/uR6gsUfdx uQ4mPdJF99LDUuCtkQue6EyggQyO4SGx8dS+1FG03rfbjYc0GgN8= Received: (qmail 679 invoked by alias); 10 Sep 2013 17:12:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 666 invoked by uid 89); 10 Sep 2013 17:12:06 -0000 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 10 Sep 2013 17:12:06 +0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=AWL, BAYES_00, KHOP_THREADED, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_NO, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 10 Sep 2013 18:12:03 +0100 Received: from [10.1.201.52] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 10 Sep 2013 18:12:01 +0100 Message-ID: <522F52E0.8040007@arm.com> Date: Tue, 10 Sep 2013 18:12:00 +0100 From: Yufeng Zhang User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org CC: Marcus Shawcroft Subject: Re: [PATCH, AArch64] Fix the pointer-typed function argument expansion in aarch64_simd_expand_args References: <522F51F6.9040109@arm.com> In-Reply-To: <522F51F6.9040109@arm.com> X-MC-Unique: 113091018120301701 X-IsSubscribed: yes Oops, now attach the correct patch and change log. Thanks, Yufeng gcc/ * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Call aarch64_simd_expand_args to update op[argc]. On 09/10/13 18:08, Yufeng Zhang wrote: > This patch fixes a number of test failures in gcc.target/aarch64/v*.c in > ILP32. > > The corresponding RTL patterns for some load/store builtins have Pmode > (i.e. DImode) specified for their address operands. However, coming > from a pointer-typed function argument, op[argc] will have SImode in > ILP32. Instead of duplicating these RTL patterns to cope with SImode > operand (which e.g. would complicate arm_neon.h), we explicitly convert > the operand to Pmode here; an address operand in a RTL shall have Pmode > anyway. Note that if op[argc] already has DImode, > convert_memory_address will simply return it diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 6816b9c..0df5b3b 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -989,6 +989,8 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, switch (thisarg) { case SIMD_ARG_COPY_TO_REG: + if (POINTER_TYPE_P (TREE_TYPE (arg[argc]))) + op[argc] = convert_memory_address (Pmode, op[argc]); /*gcc_assert (GET_MODE (op[argc]) == mode[argc]); */ if (!(*insn_data[icode].operand[argc + have_retval].predicate) (op[argc], mode[argc]))