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[AArch64] : Fix format of <su>mull<q> instruction.

Message ID 50EC2C6B.1020508@arm.com
State New
Headers show

Commit Message

Tejas Belagod Jan. 8, 2013, 2:25 p.m. UTC 
Hi,

Attached is a patch that fixes the instruction and operand separator for 
<su>mull<2> instructions from a space to a tab.

Regressed for aarch64-none-elf on trunk. OK to commit?

Thanks,
Tejas Belagod
ARM.

2013-01-08  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_<su>mult_lo_<mode>,
	aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and operand
	with tab instead of space.

Comments

Marcus Shawcroft Jan. 8, 2013, 2:54 p.m. UTC | #1 
On 8 January 2013 14:25, Tejas Belagod <tbelagod@arm.com> wrote:
>
> 2013-01-08  Tejas Belagod  <tejas.belagod@arm.com>
>
> gcc/
>         * config/aarch64/aarch64-simd.md
> (aarch64_simd_vec_<su>mult_lo_<mode>,
>         aarch64_simd_vec_<su>mult_hi_<mode>): Separate instruction and
> operand
>         with tab instead of space.
>

OK
/Marcus
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index febf71d..01348ec 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1100,7 +1100,7 @@ 
                            (match_operand:VQW 2 "register_operand" "w")
                            (match_dup 3)))))]
   "TARGET_SIMD"
-  "<su>mull %0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
+  "<su>mull\\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>"
   [(set_attr "simd_type" "simd_mull")
    (set_attr "simd_mode" "<MODE>")]
 )
@@ -1128,7 +1128,7 @@ 
 			    (match_operand:VQW 2 "register_operand" "w")
 			    (match_dup 3)))))]
   "TARGET_SIMD"
-  "<su>mull2 %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+  "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
   [(set_attr "simd_type" "simd_mull")
    (set_attr "simd_mode" "<MODE>")]
 )