From patchwork Mon Sep 10 15:05:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 182905 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 56CD32C0088 for ; Tue, 11 Sep 2012 01:06:19 +1000 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1347894380; h=Comment: DomainKey-Signature:Received:Received:Received:Received:Received: Message-ID:Date:From:User-Agent:MIME-Version:To:Subject: Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:Sender:Delivered-To; bh=hyqDJc/ N/SBZrTtX5UxlM4a1434=; b=sZzMa4Bm6REQHeyheAe/5pXvt9FBidWTq/Vxynx n43pHGGVjptIc1fZ97zssl8b97uN2g9NdASbPthjmjI2aGxr/MKWarRdNGvu+3yG uB4F76cpBVoLmPqk7VNNuFpZrayVpLdtoEptUNRGFzqXb1yFNmj66q7HyNcO6XK8 DFfI= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Message-ID:Date:From:User-Agent:MIME-Version:To:Subject:X-MC-Unique:Content-Type:X-IsSubscribed:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=j3TcE0LDHmQbL1kYnKOQ3qJwzrRT0QhC0Y9JTn3BdvucGI0FS71kQEvtKEuDp3 VB7a89eQNI7olORbz3PJRl650PMM+Aw5GO+SsCaPsAUzK+3I7Kqc9wjszCuxOkZK 8SkcvIYkAvq2VP8pXhZLDIdrHmfoc8kl85oW60lPmsFtQ=; Received: (qmail 25925 invoked by alias); 10 Sep 2012 15:06:16 -0000 Received: (qmail 25911 invoked by uid 22791); 10 Sep 2012 15:06:15 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Sep 2012 15:06:02 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 10 Sep 2012 16:06:00 +0100 Received: from [10.1.79.66] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 10 Sep 2012 16:05:58 +0100 Message-ID: <504E01D6.5090809@arm.com> Date: Mon, 10 Sep 2012 16:05:58 +0100 From: Tejas Belagod User-Agent: Thunderbird 2.0.0.18 (X11/20081120) MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" Subject: [Patch][AArch64] Split a move of Q-reg vectors contained in general regs. X-MC-Unique: 112091016060002801 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch fixes the mov pattern to split a move between general regs that contain a Q-reg vector value. Regression-tested on aarch64-none-elf. OK for aarch64-branch? Thanks, Tejas Belagod ARM. Changelog: 2012-09-10 Tejas Belagod gcc/ * config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Split Q-reg vector value move contained in general registers. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index d3f8ef2..1113b06 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -443,7 +443,7 @@ case 2: return "orr\t%0., %1., %1."; case 3: return "umov\t%0, %1.d[0]\;umov\t%H0, %1.d[1]"; case 4: return "ins\t%0.d[0], %1\;ins\t%0.d[1], %H1"; - case 5: return "mov\t%0, %1;mov\t%H0, %H1"; + case 5: return "#"; case 6: { int is_valid; @@ -475,6 +475,27 @@ (set_attr "length" "4,4,4,8,8,8,4")] ) +(define_split + [(set (match_operand:VQ 0 "register_operand" "") + (match_operand:VQ 1 "register_operand" ""))] + "TARGET_SIMD && reload_completed + && GP_REGNUM_P (REGNO (operands[0])) + && GP_REGNUM_P (REGNO (operands[1]))" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))] +{ + int rdest = REGNO (operands[0]); + int rsrc = REGNO (operands[1]); + rtx dest[2], src[2]; + + dest[0] = gen_rtx_REG (DImode, rdest); + src[0] = gen_rtx_REG (DImode, rsrc); + dest[1] = gen_rtx_REG (DImode, rdest + 1); + src[1] = gen_rtx_REG (DImode, rsrc + 1); + + aarch64_simd_disambiguate_copy (operands, dest, src, 2); +}) + (define_insn "orn3" [(set (match_operand:VDQ 0 "register_operand" "=w") (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))