diff mbox

[AVR] : avr.md code clean-up

Message ID 4F268608.90600@gjlay.de
State New
Headers show

Commit Message

Georg-Johann Lay Jan. 30, 2012, 11:59 a.m. UTC 
This is code clean-up for avr.md.

* It resolves all AS1 and AS2 macros for string insertion.
  There are plan strings now and no more needed because:

* All deprecated "* quoted-c-code" transformed to { c-code }.
  so that avr.md matches http://gcc.gnu.org/backends.html
  now, i.e. no 'b' in the avr line.

* insn-condition "optimize" or "optimize > 0" is redundant with
  combine patterns as combine does not run at -O0

* Some minor coding style changes

For the AS1/AS2 removal I used the attached awk.

Ok to apply?

Johann

	* config/avr/avr.md: Resolve all AS1 and AS2 macros.
	Transform all "* quoted-c-code" to { c-code }.
	Remove redundant test for "optimize" in combine patterns.
	Move (include "avr-dimode.md") to end of file.
/AS1/ {
	$0 = gensub (/AS1[ \t]*\(([a-z]+),([^,\)]+)\)/, "\"\\1 \\2\"", "")
}

/AS2/ {
	$0 = gensub (/AS2[ \t]*\(([a-z]+),([^,\)]+),([^,\)]+)\)/, "\"\\1 \\2,\\3\"", "")
}

{
	print;
}

Comments

Denis Chertykov Jan. 30, 2012, 7:18 p.m. UTC | #1 
2012/1/30 Georg-Johann Lay <avr@gjlay.de>:
> This is code clean-up for avr.md.
>
> * It resolves all AS1 and AS2 macros for string insertion.
>  There are plan strings now and no more needed because:
>
> * All deprecated "* quoted-c-code" transformed to { c-code }.
>  so that avr.md matches http://gcc.gnu.org/backends.html
>  now, i.e. no 'b' in the avr line.
>
> * insn-condition "optimize" or "optimize > 0" is redundant with
>  combine patterns as combine does not run at -O0
>
> * Some minor coding style changes
>
> For the AS1/AS2 removal I used the attached awk.
>
> Ok to apply?
>
> Johann
>
>        * config/avr/avr.md: Resolve all AS1 and AS2 macros.
>        Transform all "* quoted-c-code" to { c-code }.
>        Remove redundant test for "optimize" in combine patterns.
>        Move (include "avr-dimode.md") to end of file.
>

Please apply.

Denis.
diff mbox

Patch

Index: config/avr/avr.md
===================================================================
--- config/avr/avr.md	(revision 183695)
+++ config/avr/avr.md	(working copy)
@@ -1152,7 +1152,7 @@  (define_insn "addsi3"
       };
 
     if (*asm_code[which_alternative])
-      return asm_code [which_alternative];
+      return asm_code[which_alternative];
 
     return avr_out_plus (operands, NULL, NULL);
   }
@@ -1221,7 +1221,7 @@  (define_insn "addpsi3"
       };
 
     if (*asm_code[which_alternative])
-      return asm_code [which_alternative];
+      return asm_code[which_alternative];
 
     return avr_out_plus (operands, NULL, NULL);
   }
@@ -1346,13 +1346,13 @@  (define_expand "mulqi3"
 	(mult:QI (match_operand:QI 1 "register_operand" "")
 		 (match_operand:QI 2 "register_operand" "")))]
   ""
-  "{
-  if (!AVR_HAVE_MUL)
-    {
-      emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
-      DONE;
-    }
-}")
+  {
+    if (!AVR_HAVE_MUL)
+      {
+        emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
+        DONE;
+      }
+  })
 
 (define_insn "*mulqi3_enh"
   [(set (match_operand:QI 0 "register_operand" "=r")
@@ -4381,7 +4381,9 @@  (define_insn "*sbrx_branch<mode>"
 	 (label_ref (match_operand 3 "" ""))
 	 (pc)))]
   ""
-  "* return avr_out_sbxx_branch (insn, operands);"
+  {
+    return avr_out_sbxx_branch (insn, operands);
+  }
   [(set (attr "length")
 	(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
 			   (le (minus (pc) (match_dup 3)) (const_int 2046)))
@@ -4559,8 +4561,9 @@  (define_insn "difficult_branch"
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "*
-   return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
+  {
+    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
+  }
   [(set_attr "type" "branch1")
    (set_attr "cc" "clobber")])
 
@@ -4574,8 +4577,9 @@  (define_insn "rvbranch"
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-   return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
+  {
+    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
+  }
   [(set_attr "type" "branch1")
    (set_attr "cc" "clobber")])
 
@@ -4587,8 +4591,9 @@  (define_insn "difficult_rvbranch"
                       (pc)
                       (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-   return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
+  {
+    return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
+  }
   [(set_attr "type" "branch")
    (set_attr "cc" "clobber")])
 
@@ -4769,10 +4774,9 @@  (define_expand "casesi"
 	      (use (label_ref (match_dup 3)))
 	      (clobber (match_dup 6))])]
   ""
-  "
-{
-  operands[6] = gen_reg_rtx (HImode);
-}")
+  {
+    operands[6] = gen_reg_rtx (HImode);
+  })
 
 
 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -4791,7 +4795,7 @@  (define_insn "*cbi"
   [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
         (and:QI (mem:QI (match_dup 0))
                 (match_operand:QI 1 "single_zero_operand" "n")))]
-  "optimize > 0"
+  ""
   {
     operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
     return "cbi %i0,%2";
@@ -4803,7 +4807,7 @@  (define_insn "*sbi"
   [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
         (ior:QI (mem:QI (match_dup 0))
                 (match_operand:QI 1 "single_one_operand" "n")))]
-  "optimize > 0"
+  ""
   {
     operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
     return "sbi %i0,%2";
@@ -4823,8 +4827,10 @@  (define_insn "*sbix_branch"
 			  (const_int 0)])
 	 (label_ref (match_operand 3 "" ""))
 	 (pc)))]
-  "(optimize > 0)"
-  "* return avr_out_sbxx_branch (insn, operands);"
+  ""
+  {
+    return avr_out_sbxx_branch (insn, operands);
+  }
   [(set (attr "length")
 	(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
                            (le (minus (pc) (match_dup 3)) (const_int 2046)))
@@ -4843,7 +4849,7 @@  (define_insn "*sbix_branch_bit7"
 			  (const_int 0)])
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))]
-  "(optimize > 0)"
+  ""
 {
   operands[3] = operands[2];
   operands[2] = GEN_INT (7);
@@ -4870,8 +4876,10 @@  (define_insn "*sbix_branch_tmp"
 			  (const_int 0)])
 	 (label_ref (match_operand 3 "" ""))
 	 (pc)))]
-  "(optimize > 0)"
-  "* return avr_out_sbxx_branch (insn, operands);"
+  ""
+  {
+    return avr_out_sbxx_branch (insn, operands);
+  }
   [(set (attr "length")
 	(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
                            (le (minus (pc) (match_dup 3)) (const_int 2045)))
@@ -4889,7 +4897,7 @@  (define_insn "*sbix_branch_tmp_bit7"
 			  (const_int 0)])
 	 (label_ref (match_operand 2 "" ""))
 	 (pc)))]
-  "(optimize > 0)"
+  ""
 {
   operands[3] = operands[2];
   operands[2] = GEN_INT (7);
@@ -4924,26 +4932,27 @@  (define_peephole
   {
     CC_STATUS_INIT;
     if (test_hard_reg_class (ADDW_REGS, operands[0]))
-      output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
-                       AS2 (sbc,%C0,__zero_reg__) CR_TAB
-                       AS2 (sbc,%D0,__zero_reg__) "\n", operands);
+      output_asm_insn ("sbiw %0,1" CR_TAB
+                       "sbc %C0,__zero_reg__" CR_TAB
+                       "sbc %D0,__zero_reg__", operands);
     else
-      output_asm_insn (AS2 (subi,%A0,1) CR_TAB
-                       AS2 (sbc,%B0,__zero_reg__) CR_TAB
-                       AS2 (sbc,%C0,__zero_reg__) CR_TAB
-                       AS2 (sbc,%D0,__zero_reg__) "\n", operands);
+      output_asm_insn ("subi %A0,1" CR_TAB
+                       "sbc %B0,__zero_reg__" CR_TAB
+                       "sbc %C0,__zero_reg__" CR_TAB
+                       "sbc %D0,__zero_reg__", operands);
 
     switch (avr_jump_mode (operands[2], insn))
       {
       case 1:
-        return AS1 (brcc,%2);
+        return "brcc %2";
       case 2:
-        return (AS1 (brcs,.+2) CR_TAB
-                AS1 (rjmp,%2));
+        return "brcs .+2\;rjmp %2";
+      case 3:
+        return "brcs .+4\;jmp %2";
       }
 
-    return (AS1 (brcs,.+4) CR_TAB
-            AS1 (jmp,%2));
+    gcc_unreachable();
+    return "";
   })
 
 (define_peephole
@@ -4960,25 +4969,27 @@  (define_peephole
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
-{
-  CC_STATUS_INIT;
-  if (test_hard_reg_class (ADDW_REGS, operands[0]))
-    output_asm_insn (AS2 (sbiw,%0,1), operands);
-  else
-    output_asm_insn (AS2 (subi,%A0,1) CR_TAB
-		     AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
-  switch (avr_jump_mode (operands[2],insn))
-  {
-    case 1:
-      return AS1 (brcc,%2);
-    case 2:
-      return (AS1 (brcs,.+2) CR_TAB
-              AS1 (rjmp,%2));
-  }
-  return (AS1 (brcs,.+4) CR_TAB
-          AS1 (jmp,%2));
-}")
+  {
+    CC_STATUS_INIT;
+    if (test_hard_reg_class (ADDW_REGS, operands[0]))
+      output_asm_insn ("sbiw %0,1", operands);
+    else
+      output_asm_insn ("subi %A0,1" CR_TAB
+                       "sbc %B0,__zero_reg__", operands);
+
+    switch (avr_jump_mode (operands[2], insn))
+      {
+      case 1:
+        return "brcc %2";
+      case 2:
+        return "brcs .+2\;rjmp %2";
+      case 3:
+        return "brcs .+4\;jmp %2";
+      }
+
+    gcc_unreachable();
+    return "";
+  })
 
 (define_peephole
   [(set (match_operand:QI 0 "d_register_operand" "")
@@ -4992,23 +5003,26 @@  (define_peephole
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
   ""
-  "*
-{
-  CC_STATUS_INIT;
-  cc_status.value1 = operands[0];
-  cc_status.flags |= CC_OVERFLOW_UNUSABLE;
-  output_asm_insn (AS2 (subi,%A0,1), operands);
-  switch (avr_jump_mode (operands[1],insn))
-  {
-    case 1:
-      return AS1 (brcc,%1);
-    case 2:
-      return (AS1 (brcs,.+2) CR_TAB
-              AS1 (rjmp,%1));
-  }
-  return (AS1 (brcs,.+4) CR_TAB
-          AS1 (jmp,%1));
-}")
+  {
+    CC_STATUS_INIT;
+    cc_status.value1 = operands[0];
+    cc_status.flags |= CC_OVERFLOW_UNUSABLE;
+
+    output_asm_insn ("subi %A0,1", operands);
+
+    switch (avr_jump_mode (operands[1], insn))
+      {
+      case 1:
+        return "brcc %1";
+      case 2:
+        return "brcs .+2\;rjmp %1";
+      case 3:
+        return "brcs .+4\;jmp %1";
+      }
+
+    gcc_unreachable();
+    return "";
+  })
 
 
 (define_peephole ; "*cpse.eq"
@@ -5947,8 +5961,6 @@  (define_insn_and_split "*extzv.qihi1"
     operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
   })
 
-(include "avr-dimode.md")
-
 (define_insn_and_split "*extzv.qihi2"
   [(set (match_operand:HI 0 "register_operand"                      "=r")
         (zero_extend:HI 
@@ -5968,3 +5980,6 @@  (define_insn_and_split "*extzv.qihi2"
     operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
     operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
   })
+
+
+(include "avr-dimode.md")