From patchwork Fri May 27 16:36:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 97706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 83EB0B6F8B for ; Sat, 28 May 2011 02:36:49 +1000 (EST) Received: (qmail 15452 invoked by alias); 27 May 2011 16:36:44 -0000 Received: (qmail 15332 invoked by uid 22791); 27 May 2011 16:36:43 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 27 May 2011 16:36:28 +0000 Received: (qmail 20505 invoked from network); 27 May 2011 16:36:27 -0000 Received: from unknown (HELO ?192.168.0.100?) (ams@127.0.0.2) by mail.codesourcery.com with ESMTPA; 27 May 2011 16:36:27 -0000 Message-ID: <4DDFD307.6010808@codesourcery.com> Date: Fri, 27 May 2011 17:36:23 +0100 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org, patches@linaro.org Subject: [PATCH][ARM] add support for some missing 16-bit multiplication insns Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi all, This patch adds support for the ARM SMLALTB, SMLALTT, SMLATB, and SMLATT instructions. These instructions do HImode -> DI/SImode widening multiply-and-accumulate with one or both operands taken from the top 16 bits of the source register. Note that this patch won't do much until my other patch for canonical mult patterns is applied. OK? Andrew 2011-05-27 Andrew Stubbs gcc/ * config/arm/arm.md (*maddhidi4tb, *maddhidi4tt): New define_insns. (*maddhisi4tb, *maddhisi4tt): New define_insns. gcc/testsuite/ * gcc.target/arm/smlatb-1.c: New file. * gcc.target/arm/smlatt-1.c: New file. * gcc.target/arm/smlaltb-1.c: New file. * gcc.target/arm/smlaltt-1.c: New file. --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1815,6 +1815,36 @@ (set_attr "predicable" "yes")] ) +;; Note: there is no maddhisi4ibt because this one is canonical form +(define_insn "*maddhisi4tb" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (mult:SI (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16)) + (sign_extend:SI + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlatb%?\\t%0, %1, %2, %3" + [(set_attr "insn" "smlaxy") + (set_attr "predicable" "yes")] +) + +(define_insn "*maddhisi4tt" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (plus:SI (mult:SI (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16)) + (ashiftrt:SI + (match_operand:SI 2 "s_register_operand" "r") + (const_int 16))) + (match_operand:SI 3 "s_register_operand" "r")))] + "TARGET_DSP_MULTIPLY" + "smlatt%?\\t%0, %1, %2, %3" + [(set_attr "insn" "smlaxy") + (set_attr "predicable" "yes")] +) + (define_insn "*maddhidi4" [(set (match_operand:DI 0 "s_register_operand" "=r") (plus:DI @@ -1828,6 +1858,39 @@ [(set_attr "insn" "smlalxy") (set_attr "predicable" "yes")]) +;; Note: there is no maddhidi4ibt because this one is canonical form +(define_insn "*maddhidi4tb" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI + (mult:DI (sign_extend:DI + (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16))) + (sign_extend:DI + (match_operand:HI 2 "s_register_operand" "r"))) + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlaltb%?\\t%Q0, %R0, %1, %2" + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + +(define_insn "*maddhidi4tt" + [(set (match_operand:DI 0 "s_register_operand" "=r") + (plus:DI + (mult:DI (sign_extend:DI + (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16))) + (sign_extend:DI + (ashiftrt:SI + (match_operand:SI 2 "s_register_operand" "r") + (const_int 16)))) + (match_operand:DI 3 "s_register_operand" "0")))] + "TARGET_DSP_MULTIPLY" + "smlaltt%?\\t%Q0, %R0, %1, %2" + [(set_attr "insn" "smlalxy") + (set_attr "predicable" "yes")]) + (define_expand "mulsf3" [(set (match_operand:SF 0 "s_register_operand" "") (mult:SF (match_operand:SF 1 "s_register_operand" "") --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlaltb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +long long int +foo (long long x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltb" } } */ --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlaltt-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +long long int +foo (long long x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlaltt" } } */ --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlatb-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +int +foo (int x, int in) +{ + short a = in & 0xffff; + short b = (in & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatb" } } */ --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/smlatt-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +int +foo (int x, int in1, int in2) +{ + short a = (in1 & 0xffff0000) >> 16; + short b = (in2 & 0xffff0000) >> 16; + + return x + b * a; +} + +/* { dg-final { scan-assembler "smlatt" } } */