From patchwork Wed Dec 8 16:42:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 74746 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 201C8B70A3 for ; Thu, 9 Dec 2010 03:42:44 +1100 (EST) Received: (qmail 21049 invoked by alias); 8 Dec 2010 16:42:43 -0000 Received: (qmail 21035 invoked by uid 22791); 8 Dec 2010 16:42:42 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 08 Dec 2010 16:42:38 +0000 Received: (qmail 30840 invoked from network); 8 Dec 2010 16:42:35 -0000 Received: from unknown (HELO ?192.168.0.102?) (yao@127.0.0.2) by mail.codesourcery.com with ESMTPA; 8 Dec 2010 16:42:35 -0000 Message-ID: <4CFFB571.9080308@codesourcery.com> Date: Thu, 09 Dec 2010 00:42:25 +0800 From: Yao Qi User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.1.15) Gecko/20101027 Thunderbird/3.0.10 MIME-Version: 1.0 To: gcc-patches@gcc.gnu.org Subject: [patch, arm] Prefer LO_REG registers in regrename X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This patch is to implement to targethook preferred_rename_class, in order to prefer LO_REGS registers over GENERAL_REGS registers in Thumb-2. EEMBC doesn't show speed improvements, but code size of some benchmarks in EEMBC is reduced by 0.1% ~ 0.2%. Regression tested on '2010-11-30' trunk. OK for mainline? gcc/ * config/arm/arm.c (arm_preferred_rename_class): Implement targethook PREFERRED_RENAME_CLASS. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index afca3c6..1b27f00 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -246,6 +246,7 @@ static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, const_tree type, int misalignment, bool is_packed); +static reg_class_t arm_preferred_rename_class (reg_class_t class) /* Table of machine attributes. */ @@ -578,6 +579,10 @@ static const struct default_options arm_option_optimization_table[] = #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \ arm_builtin_support_vector_misalignment +#undef TARGET_PREFERRED_RENAME_CLASS +#define TARGET_PREFERRED_RENAME_CLASS \ + arm_preferred_rename_class + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -23264,4 +23269,16 @@ arm_builtin_support_vector_misalignment (enum machine_mode mode, is_packed); } +static reg_class_t +arm_preferred_rename_class (reg_class_t class) +{ + /* thumb-2 instructions using LO_REGS may be smaller than instructions + using GENERIC_REGS. During register rename pass, we prefer LO_REGS, + and code size can be reduced. */ + if (TARGET_THUMB2 && class == GENERAL_REGS) + return LO_REGS; + else + return default_preferred_rename_class (class); +} + #include "gt-arm.h"