From patchwork Thu Jun 24 22:01:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catherine Moore X-Patchwork-Id: 56861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E60A9B6F29 for ; Fri, 25 Jun 2010 08:02:40 +1000 (EST) Received: (qmail 32535 invoked by alias); 24 Jun 2010 22:02:38 -0000 Received: (qmail 32295 invoked by uid 22791); 24 Jun 2010 22:02:36 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 24 Jun 2010 22:02:27 +0000 Received: (qmail 22694 invoked from network); 24 Jun 2010 22:02:25 -0000 Received: from unknown (HELO ?192.168.89.128?) (clm@127.0.0.2) by mail.codesourcery.com with ESMTPA; 24 Jun 2010 22:02:25 -0000 Message-ID: <4C23D5A8.9040609@codesourcery.com> Date: Thu, 24 Jun 2010 18:01:12 -0400 From: Catherine Moore User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: Richard Sandiford CC: "Fu, Chao-Ying" , Catherine Moore , "Maciej W. Rozycki" , gcc-patches Subject: [patch] Add new alu_type and logical_type attributes for MIPS. Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi Richard, This patch adds the alu_type attribute and the logical_type attribute. The purpose of this patch is to lay the groundwork for the removal of the micromips_type attribute in the pending microMIPS patch. Does this look okay to install? Test results looked good for the mips-sde-elf target. Thanks, Catherine 2010-06-24 Catherine Moore * config/mips/mips.md (alu_type): New attribute. (logical_type): New attribute. (type): Infer type from alu_type and logical_type. (*add3, *add3_mips16, *addsi3_extended, *baddu_si_eb, *baddu_si_el, *baddu_di, sub3, *subsi3_extended, negsi2, negdi2, *low, *low_mips16): Set alu_type instead of type. (*ior3, *ior3_mips16, xor3, *nor3, *zero_extend_trunc, *zero_extendhi_truncqi: Set logical_type instead of type. Index: mips.md =================================================================== --- mips.md (revision 161336) +++ mips.md (working copy) @@ -199,6 +199,12 @@ (define_attr "move_type" shift_shift,lui_movf" (const_string "unknown")) +(define_attr "alu_type" "unknown,add,sub" + (const_string "unknown")) + +(define_attr "logical_type" "unknown,not,and,or,xor" + (const_string "unknown")) + ;; Main data type used by the insn (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW" (const_string "unknown")) @@ -275,6 +281,14 @@ (define_attr "type" (cond [(eq_attr "jal" "!unset") (const_string "call") (eq_attr "got" "load") (const_string "load") + (eq_attr "alu_type" "add") (const_string "arith") + (eq_attr "alu_type" "sub") (const_string "arith") + + (eq_attr "logical_type" "not") (const_string "logical") + (eq_attr "logical_type" "and") (const_string "logical") + (eq_attr "logical_type" "or") (const_string "logical") + (eq_attr "logical_type" "xor") (const_string "logical") + ;; If a doubleword move uses these expensive instructions, ;; it is usually better to schedule them in the same way ;; as the singleword form, rather than as "multi". @@ -978,7 +992,7 @@ (define_insn "*add3" "@ addu\t%0,%1,%2 addiu\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "add") (set_attr "mode" "")]) (define_insn "*add3_mips16" @@ -992,7 +1006,7 @@ (define_insn "*add3_mips16" addiu\t%0,%2 addiu\t%0,%1,%2 addu\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "add") (set_attr "mode" "") (set_attr_alternative "length" [(if_then_else (match_operand 2 "m16_simm8_8") @@ -1130,7 +1144,7 @@ (define_insn "*addsi3_extended" "@ addu\t%0,%1,%2 addiu\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "add") (set_attr "mode" "SI")]) ;; Split this insn so that the addiu splitters can have a crack at it. @@ -1145,7 +1159,7 @@ (define_insn_and_split "*addsi3_extended "&& reload_completed" [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))] { operands[3] = gen_lowpart (SImode, operands[0]); } - [(set_attr "type" "arith") + [(set_attr "alu_type" "add") (set_attr "mode" "SI") (set_attr "extended_mips16" "yes")]) @@ -1159,7 +1173,7 @@ (define_insn "*baddu_si_eb" (match_operand:SI 2 "register_operand" "d")) 3)))] "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" - [(set_attr "type" "arith")]) + [(set_attr "alu_type" "add")]) (define_insn "*baddu_si_el" [(set (match_operand:SI 0 "register_operand" "=d") @@ -1169,7 +1183,7 @@ (define_insn "*baddu_si_el" (match_operand:SI 2 "register_operand" "d")) 0)))] "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" "baddu\\t%0,%1,%2" - [(set_attr "type" "arith")]) + [(set_attr "alu_type" "add")]) (define_insn "*baddu_di" [(set (match_operand:GPR 0 "register_operand" "=d") @@ -1179,7 +1193,7 @@ (define_insn "*baddu_di" (match_operand:DI 2 "register_operand" "d")))))] "ISA_HAS_BADDU && TARGET_64BIT" "baddu\\t%0,%1,%2" - [(set_attr "type" "arith")]) + [(set_attr "alu_type" "add")]) ;; ;; .................... @@ -1204,7 +1218,7 @@ (define_insn "sub3" (match_operand:GPR 2 "register_operand" "d")))] "" "subu\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "sub") (set_attr "mode" "")]) (define_insn "*subsi3_extended" @@ -1214,7 +1228,7 @@ (define_insn "*subsi3_extended" (match_operand:SI 2 "register_operand" "d"))))] "TARGET_64BIT" "subu\t%0,%1,%2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "sub") (set_attr "mode" "DI")]) ;; @@ -2483,7 +2497,7 @@ (define_insn "negsi2" else return "subu\t%0,%.,%1"; } - [(set_attr "type" "arith") + [(set_attr "alu_type" "sub") (set_attr "mode" "SI")]) (define_insn "negdi2" @@ -2491,7 +2505,7 @@ (define_insn "negdi2" (neg:DI (match_operand:DI 1 "register_operand" "d")))] "TARGET_64BIT && !TARGET_MIPS16" "dsubu\t%0,%.,%1" - [(set_attr "type" "arith") + [(set_attr "alu_type" "sub") (set_attr "mode" "DI")]) ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as @@ -2516,7 +2530,7 @@ (define_insn "one_cmpl2" else return "nor\t%0,%.,%1"; } - [(set_attr "type" "logical") + [(set_attr "logical_type" "not") (set_attr "mode" "")]) ;; @@ -2638,7 +2652,7 @@ (define_insn "*ior3" "@ or\t%0,%1,%2 ori\t%0,%1,%x2" - [(set_attr "type" "logical") + [(set_attr "logical_type" "or") (set_attr "mode" "")]) (define_insn "*ior3_mips16" @@ -2647,7 +2661,7 @@ (define_insn "*ior3_mips16" (match_operand:GPR 2 "register_operand" "d")))] "TARGET_MIPS16" "or\t%0,%2" - [(set_attr "type" "logical") + [(set_attr "logical_type" "or") (set_attr "mode" "")]) (define_expand "xor3" @@ -2665,7 +2679,7 @@ (define_insn "" "@ xor\t%0,%1,%2 xori\t%0,%1,%x2" - [(set_attr "type" "logical") + [(set_attr "logical_type" "or") (set_attr "mode" "")]) (define_insn "" @@ -2678,6 +2692,7 @@ (define_insn "" cmpi\t%1,%2 cmp\t%1,%2" [(set_attr "type" "logical,arith,arith") + (set_attr "logical_type" "or,unknown,unknown") (set_attr "mode" "") (set_attr_alternative "length" [(const_int 4) @@ -2692,7 +2707,7 @@ (define_insn "*nor3" (not:GPR (match_operand:GPR 2 "register_operand" "d"))))] "!TARGET_MIPS16" "nor\t%0,%1,%2" - [(set_attr "type" "logical") + [(set_attr "logical_type" "or") (set_attr "mode" "")]) ;; @@ -2910,7 +2925,7 @@ (define_insn "*zero_extend_tru operands[2] = GEN_INT (GET_MODE_MASK (mode)); return "andi\t%0,%1,%x2"; } - [(set_attr "type" "logical") + [(set_attr "logical_type" "and") (set_attr "mode" "")]) (define_insn "*zero_extendhi_truncqi" @@ -2919,7 +2934,7 @@ (define_insn "*zero_extendhi_truncqi" (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] "TARGET_64BIT && !TARGET_MIPS16" "andi\t%0,%1,0xff" - [(set_attr "type" "logical") + [(set_attr "logical_type" "and") (set_attr "mode" "HI")]) ;; @@ -3851,7 +3866,7 @@ (define_insn "*low" (match_operand:P 2 "immediate_operand" "")))] "!TARGET_MIPS16" "addiu\t%0,%1,%R2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "add") (set_attr "mode" "")]) (define_insn "*low_mips16" @@ -3860,7 +3875,7 @@ (define_insn "*low_mips16" (match_operand:P 2 "immediate_operand" "")))] "TARGET_MIPS16" "addiu\t%0,%R2" - [(set_attr "type" "arith") + [(set_attr "alu_type" "add") (set_attr "mode" "") (set_attr "extended_mips16" "yes")])