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Thu, 09 Jul 2020 04:02:48 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06942lVd10486394 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Jul 2020 04:02:47 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 237FB124055; Thu, 9 Jul 2020 04:02:47 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 823B6124054; Thu, 9 Jul 2020 04:02:46 +0000 (GMT) Received: from [9.160.107.156] (unknown [9.160.107.156]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Thu, 9 Jul 2020 04:02:46 +0000 (GMT) To: Segher Boessenkool , David Edelsohn Subject: [PATCH] rs6000: Allow MMA built-in initialization regardless of compiler options Message-ID: <3af10fe8-a4c9-a7ef-9511-9e133d430b32@linux.ibm.com> Date: Wed, 8 Jul 2020 23:02:45 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-08_19:2020-07-08, 2020-07-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007090026 X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Peter Bergner via Gcc-patches From: Peter Bergner Reply-To: Peter Bergner Cc: Bill Schmidt , GCC Patches Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" PR96125 shows a bug when we try to use an MMA built-in within a function that uses #pragma target/attribute target to enable power10 code generation and the -mcpu= command line option is pre-power10. The problem is that we only initialize built-ins once, fairly early, when the command line options are in force. If the -mcpu= is pre-power10, then we fail to initialize the MMA built-ins at all and so they are not available to call in a #pragma target/attribute target function. The patch below basically always (on server type cpus) initializes the MMA built-ins so we can use them in #pragma target/attribute target functions. The patch below fixes the bug and is currently in the middle of testing. Is this ok for trunk assuming the bootstrap and regression testing show no regressions? This also affects GCC10, so I'd like to backport this before the release. Ok there too after it sits on trunk a day or two? Peter gcc/ PR target/96125 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Define the MMA specific types __vector_quad and __vector_pair, and initialize the MMA built-ins if TARGET_EXTRA_BUILTINS is set. (mma_init_builtins): Don't test for mask set in rs6000_builtin_mask. Remove now unneeded mask variable. * config/rs6000/rs6000.c (rs6000_option_override_internal): Add the OPTION_MASK_MMA flag for power10 if not already set. gcc/testsuite/ PR target/96125 * gcc.target/powerpc/pr96125.c: New test. diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 8e7bb54c73d..883c66810e6 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -12572,7 +12572,7 @@ rs6000_init_builtins (void) ieee128_float_type_node = ibm128_float_type_node = long_double_type_node; /* Vector pair and vector quad support. */ - if (TARGET_MMA) + if (TARGET_EXTRA_BUILTINS) { tree oi_uns_type = make_unsigned_type (256); vector_pair_type_node = build_distinct_type_copy (oi_uns_type); @@ -12648,13 +12648,14 @@ rs6000_init_builtins (void) pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel", pixel_type_node, 8); - /* Create Altivec and VSX builtins on machines with at least the + /* Create Altivec, VSX and MMA builtins on machines with at least the general purpose extensions (970 and newer) to allow the use of the target attribute. */ if (TARGET_EXTRA_BUILTINS) - altivec_init_builtins (); - if (TARGET_MMA) - mma_init_builtins (); + { + altivec_init_builtins (); + mma_init_builtins (); + } if (TARGET_HTM) htm_init_builtins (); @@ -13388,20 +13389,12 @@ mma_init_builtins (void) for (unsigned i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++) { tree op[MAX_MMA_OPERANDS], type; - HOST_WIDE_INT mask = d->mask; unsigned icode = (unsigned) d->icode; unsigned attr = rs6000_builtin_info[d->code].attr; int attr_args = (attr & RS6000_BTC_OPND_MASK); bool gimple_func = (attr & RS6000_BTC_GIMPLE); unsigned nopnds = 0; - if ((mask & rs6000_builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "mma_builtin, skip binary %s\n", d->name); - continue; - } - if (d->name == 0) { if (TARGET_DEBUG_BUILTIN) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fef72884b31..15af9b230e6 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4264,8 +4264,12 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_PCREL; } + /* Enable -mmma by default on power10 systems. */ + if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_MMA) == 0) + rs6000_isa_flags |= OPTION_MASK_MMA; + /* Turn off vector pair/mma options on non-power10 systems. */ - if (!TARGET_POWER10 && TARGET_MMA) + else if (!TARGET_POWER10 && TARGET_MMA) { if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) error ("%qs requires %qs", "-mmma", "-mcpu=power10"); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index bbd8060e143..ea2c89eb6b3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -577,7 +577,8 @@ extern int rs6000_vector_align[]; || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ || TARGET_VSX \ - || TARGET_HARD_FLOAT) + || TARGET_HARD_FLOAT \ + || TARGET_MMA) /* E500 cores only support plain "sync", not lwsync. */ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ diff --git a/gcc/testsuite/gcc.target/powerpc/pr96125.c b/gcc/testsuite/gcc.target/powerpc/pr96125.c new file mode 100644 index 00000000000..1fcc78aec11 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr96125.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ + +void +__attribute__((target("cpu=power10"))) +test0 (__vector_quad *dst) +{ + __vector_quad acc; + __builtin_mma_xxsetaccz (&acc); + *dst = acc; +} + +void +test1 (__vector_quad *dst) +{ + __vector_quad acc; + __builtin_mma_xxsetaccz (&acc); /* { dg-error "'__builtin_mma_xxsetaccz' requires the '-mmma' option" } */ + *dst = acc; +} + +#pragma GCC target("cpu=power10") +void +test2 (__vector_quad *dst) +{ + __vector_quad acc; + __builtin_mma_xxsetaccz (&acc); + *dst = acc; +} + +void +test3 (__vector_quad *dst) +{ + __vector_quad acc; + __builtin_mma_xxsetaccz (&acc); + *dst = acc; +} + +#pragma GCC reset_options +void +test4 (__vector_quad *dst) +{ + __vector_quad acc; + __builtin_mma_xxmfacc (&acc); /* { dg-error "'__builtin_mma_xxmfacc' requires the '-mmma' option" } */ + *dst = acc; +} +