diff mbox series

[committed] amdgcn: Allow V64DFmode min/max reductions

Message ID 3a1a46f1-67e8-3097-3102-99e91c3423c9@codesourcery.com
State New
Headers show
Series [committed] amdgcn: Allow V64DFmode min/max reductions | expand

Commit Message

Andrew Stubbs Jan. 26, 2021, 10:29 a.m. UTC 
This patch fixes and AMD GCN bug in which attempting to use DFmode 
vector reductions would cause an ICE.

There's no reason not to allow the reductions, so we simply enable them 
thusly.

Andrew

Comments

Andrew Stubbs Jan. 26, 2021, 11:35 a.m. UTC | #1 
Now backported to devel/omp/gcc-10.

On 26/01/2021 10:29, Andrew Stubbs wrote:
> This patch fixes and AMD GCN bug in which attempting to use DFmode 
> vector reductions would cause an ICE.
> 
> There's no reason not to allow the reductions, so we simply enable them 
> thusly.
> 
> Andrew
diff mbox series

Patch

amdgcn: Allow V64DFmode min/max reductions

I don't know why these were disabled. There're no direct min/max DPP
instructions for this mode, but the "use moves" strategy works fine.

gcc/ChangeLog:

	* config/gcn/gcn.c (gcn_expand_reduc_scalar): Use move instructions
	for V64DFmode min/max reductions.

diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 3b1762efd3a..2351b24a4d5 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -4251,7 +4251,8 @@  gcn_expand_reduc_scalar (machine_mode mode, rtx src, int unspec)
 		      || unspec == UNSPEC_SMAX_DPP_SHR
 		      || unspec == UNSPEC_UMIN_DPP_SHR
 		      || unspec == UNSPEC_UMAX_DPP_SHR)
-		     && mode == V64DImode)
+		     && (mode == V64DImode
+			 || mode == V64DFmode))
 		    || (unspec == UNSPEC_PLUS_DPP_SHR
 			&& mode == V64DFmode));
   rtx_code code = (unspec == UNSPEC_SMIN_DPP_SHR ? SMIN