From patchwork Mon Jun 27 14:58:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiong Wang X-Patchwork-Id: 641067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rdXB66dmlz9t1W for ; Tue, 28 Jun 2016 00:58:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=URQLfCRf; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=p+Bi7Ajr7A8BWrNjQ RRXEKoHBeYBmzF1o1wLp1rrItg9uGHyuTGpwk1hOBM1deYZbsf/6/14VQOvq1UdS nSSHqqNYuqtWQyqXZN/NlWxU5MI7PCKSo/4ad3DBPnpeWoFBq8idqrmTL7e6EYKZ Zp9035nN/5KYPzlPJrgf6bgy+c= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=IKkV49sbUttU/bQ3R6FbD0h 9TVQ=; b=URQLfCRfut+LN3uh1IIXozkfF46Ukfvf+gZRlsfFI2bQli0ag3+4Fx1 E1wMlZCDvZuHeodqMB3gTtzmG28Db0AxNCel+k9iAc0td5+0K6OB860jWF2Nc90/ dqqtMWmPlV1uQtwwDDDLPYAnH6CS+Y4LXcWUOThWaviG2N4LCEv4= Received: (qmail 59261 invoked by alias); 27 Jun 2016 14:58:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59247 invoked by uid 89); 27 Jun 2016 14:58:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=135, 6, 1356, Large, simd X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 27 Jun 2016 14:58:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CD9702F for ; Mon, 27 Jun 2016 07:58:53 -0700 (PDT) Received: from [10.2.206.198] (e104437-lin.cambridge.arm.com [10.2.206.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 221F13F41F for ; Mon, 27 Jun 2016 07:58:01 -0700 (PDT) Subject: Re: [AArch64] ARMv8.2 command line and feature macros support To: GCC Patches References: <8fd20f47-7f86-0bec-be43-87903502d696@foss.arm.com> From: Jiong Wang Message-ID: <39254e41-2963-bf5a-a359-41a64dc0701e@foss.arm.com> Date: Mon, 27 Jun 2016 15:58:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <8fd20f47-7f86-0bec-be43-87903502d696@foss.arm.com> X-IsSubscribed: yes On 07/06/16 09:46, Jiong Wang wrote: > 2016-06-07 Matthew Wahab > Jiong Wang > > * config/aarch64/aarch64-arches.def: Add "armv8.2-a". > * config/aarch64/aarch64.h (AARCH64_FL_V8_2): New. > (AARCH64_FL_F16): New. > (AARCH64_FL_FOR_ARCH8_2): New. > (AARCH64_ISA_8_2): New. > (AARCH64_ISA_F16): New. > (TARGET_FP_F16INST): New. > (TARGET_SIMD_F16INST): New. > * config/aarch64/aarch64-option-extensions.def: New entry for > "fp16". > * config/aarch64/aarch64-c.c (arch64_update_cpp_builtins): > Conditionally define > __ARM_FEATURE_FP16_SCALAR_ARITHMETIC and > __ARM_FEATURE_FP16_VECTOR_ARITHMETIC. > * doc/invoke.texi (AArch64 Options): Document "armv8.2-a" and > "fp16". > This is a updated version of this patch, the updates are: * When enabling "fp16" also enables "fp". * When disabling "fp" also disables "fp16". * When disabling "fp16" only disables "fp16". OK for trunk? 2016-06-27 Matthew Wahab Jiong Wang * config/aarch64/aarch64-arches.def: Add "armv8.2-a". * config/aarch64/aarch64.h (AARCH64_FL_V8_2): New. (AARCH64_FL_F16): New. (AARCH64_FL_FOR_ARCH8_2): New. (AARCH64_ISA_8_2): New. (AARCH64_ISA_F16): New. (TARGET_FP_F16INST): New. (TARGET_SIMD_F16INST): New. * config/aarch64/aarch64-option-extensions.def ("fp16"): New entry. ("fp"): Disabling "fp" also disables "fp16". * config/aarch64/aarch64-c.c (arch64_update_cpp_builtins): Conditionally define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC and __ARM_FEATURE_FP16_VECTOR_ARITHMETIC. * doc/invoke.texi (AArch64 Options): Document "armv8.2-a" and "fp16". diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 1e9d90b..7dcf140 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -32,4 +32,5 @@ AARCH64_ARCH("armv8-a", generic, 8A, 8, AARCH64_FL_FOR_ARCH8) AARCH64_ARCH("armv8.1-a", generic, 8_1A, 8, AARCH64_FL_FOR_ARCH8_1) +AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2) diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index e64dc76..3380ed6 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -95,6 +95,11 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) else cpp_undef (pfile, "__ARM_FP"); + aarch64_def_or_undef (TARGET_FP_F16INST, + "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", pfile); + aarch64_def_or_undef (TARGET_SIMD_F16INST, + "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", pfile); + aarch64_def_or_undef (TARGET_SIMD, "__ARM_FEATURE_NUMERIC_MAXMIN", pfile); aarch64_def_or_undef (TARGET_SIMD, "__ARM_NEON", pfile); diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index e8706d1..a10ccf2 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -39,8 +39,8 @@ that are required. Their order is not important. */ /* Enabling "fp" just enables "fp". - Disabling "fp" also disables "simd", "crypto". */ -AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO, "fp") + Disabling "fp" also disables "simd", "crypto" and "fp16". */ +AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16, "fp") /* Enabling "simd" also enables "fp". Disabling "simd" also disables "crypto". */ @@ -55,3 +55,7 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, "crc32") /* Enabling or disabling "lse" only changes "lse". */ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, "atomics") + +/* Enabling "fp16" also enables "fp". + Disabling "fp16" just disables "fp16". */ +AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fp16") diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index b15c23f0..d715da7 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -135,6 +135,8 @@ extern unsigned aarch64_architecture_version; /* ARMv8.1 architecture extensions. */ #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ #define AARCH64_FL_V8_1 (1 << 5) /* Has ARMv8.1 extensions. */ +#define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2 features. */ +#define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2 FP16 extensions. */ /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -146,6 +148,8 @@ extern unsigned aarch64_architecture_version; #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) #define AARCH64_FL_FOR_ARCH8_1 \ (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1) +#define AARCH64_FL_FOR_ARCH8_2 \ + (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) /* Macros to test ISA flags. */ @@ -155,6 +159,8 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_V8_1) +#define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) +#define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) @@ -165,6 +171,10 @@ extern unsigned aarch64_architecture_version; /* Atomic instructions that can be enabled through the +lse extension. */ #define TARGET_LSE (AARCH64_ISA_LSE) +/* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ +#define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) +#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) + /* Make sure this is always defined so we don't have to check for ifdefs but rather use normal ifs. */ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index aa11209..d44bbc0 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13035,7 +13035,10 @@ more feature modifiers. This option has the form @option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}. The permissible values for @var{arch} are @samp{armv8-a}, -@samp{armv8.1-a} or @var{native}. +@samp{armv8.1-a}, @samp{armv8.2-a} or @var{native}. + +The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler +support for the ARMv8.2 architecture extensions. The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler support for the ARMv8.1 architecture extension. In particular, it @@ -13140,6 +13143,8 @@ instructions. This is on by default for all possible values for options @item lse Enable Large System Extension instructions. This is on by default for @option{-march=armv8.1-a}. +@item fp16 +Enable FP16 extension. @end table