From patchwork Fri Jan 29 10:31:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Kumar Agarwal X-Patchwork-Id: 575568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2B15814017E for ; Fri, 29 Jan 2016 21:31:49 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=V+BeQqJK; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=rCGrqiFMWZxlNRQzOXNz3kIzO2x+/6sTvB+hbQX1A8VhrdNhzy thX4OVLkB+APCQlsUVSlg9jNJO5k1y6vfgLX9QAMJY3ikkUhLF/1X+u+CCpyUE/7 GSwZMk1VZmeJrDOjLW6BQ/a9f8nUN2Pf10yEInT8Q8EX9C+SaYjUYIxEA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=48a3IU7IsVomClMB7ZriWGQuk4M=; b=V+BeQqJK1ZtGE+/278sa prH1b805NAIEtcyRO/znu3WcfjmFsxfrTNKwQWrg7MJR/s9TmAz9Zk7kuFob2uti HEFhXCMvUXCV4Dqh/nKcf4NbmxC0puJ8E2fr6XaFB6mdKKX92cqPAoKuMBQoZw0Q v7Cu+7YTn6D18yNF0u4Umj0= Received: (qmail 52168 invoked by alias); 29 Jan 2016 10:31:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 52158 invoked by uid 89); 29 Jan 2016 10:31:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=achieved, H*r:Fri, 1.7.1, UD:microblaze.c X-HELO: NAM02-SN1-obe.outbound.protection.outlook.com Received: from mail-sn1nam02on0052.outbound.protection.outlook.com (HELO NAM02-SN1-obe.outbound.protection.outlook.com) (104.47.36.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA256 encrypted) ESMTPS; Fri, 29 Jan 2016 10:31:39 +0000 Received: from SN1NAM02FT035.eop-nam02.prod.protection.outlook.com (10.152.72.52) by SN1NAM02HT120.eop-nam02.prod.protection.outlook.com (10.152.72.190) with Microsoft SMTP Server (TLS) id 15.1.355.15; Fri, 29 Jan 2016 10:31:37 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; gcc.gnu.org; dkim=none (message not signed) header.d=none; gcc.gnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by SN1NAM02FT035.mail.protection.outlook.com (10.152.72.145) with Microsoft SMTP Server (TLS) id 15.1.355.15 via Frontend Transport; Fri, 29 Jan 2016 10:31:36 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:48995 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1aP6L2-0004Ms-39 for gcc-patches@gcc.gnu.org; Fri, 29 Jan 2016 02:31:36 -0800 Received: from [127.0.0.1] (helo=xsj-smtp-dlp2.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1aP6L1-0000Pc-Ug for gcc-patches@gcc.gnu.org; Fri, 29 Jan 2016 02:31:35 -0800 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u0TAVZCB030275 for ; Fri, 29 Jan 2016 02:31:35 -0800 Received: from [172.22.159.26] (helo=XAP-PVEXCAS02.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1aP6L0-0000PQ-QI for gcc-patches@gcc.gnu.org; Fri, 29 Jan 2016 02:31:35 -0800 Received: from XAP-PVEXMBX02.xlnx.xilinx.com ([fe80::6c95:7dae:8014:5ca1]) by XAP-PVEXCAS02.xlnx.xilinx.com ([::1]) with mapi id 14.03.0248.002; Fri, 29 Jan 2016 18:31:33 +0800 From: Ajit Kumar Agarwal To: GCC Patches CC: Vinod Kathail , Shail Aditya Gupta , Vidhumouli Hunsigida , "Nagaraju Mekala" Subject: [Patch, microblaze]: Better register allocation to minimize the spill and fetch. Date: Fri, 29 Jan 2016 10:31:33 +0000 Message-ID: <37378DC5BCD0EE48BA4B082E0B55DFAA429ED1AB@XAP-PVEXMBX02.xlnx.xilinx.com> MIME-Version: 1.0 X-RCIS-Action: ALLOW X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(189002)(377424004)(199003)(55846006)(19580405001)(4326007)(512954002)(87936001)(99936001)(5260100001)(4610100001)(5890100001)(84326002)(586003)(450100001)(92566002)(63266004)(86362001)(2906002)(5004730100002)(5003600100002)(2900100001)(1096002)(110136002)(4001430100002)(107886002)(2476003)(229853001)(11100500001)(6116002)(5001960100002)(2930100002)(2920100001)(568964002)(3846002)(54356999)(102836003)(106466001)(260700001)(19580395003)(50986999)(6806005)(5008740100001)(33656002)(5250100002)(1220700001)(300700001)(189998001)(107986001)(142933001); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1NAM02HT120; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; MLV:sfv; MX:1; A:1; LANG:en; X-MS-Office365-Filtering-Correlation-Id: 32ca080e-b79e-4abc-e636-08d328975ddf X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(8251501002); SRVR:SN1NAM02HT120; X-Microsoft-Antispam-PRVS: <173686c2354d44f5a228bc99861949b8@SN1NAM02HT120.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(102415267)(102615245)(601004)(2401047)(13018025)(8121501046)(13023025)(13017025)(13015025)(13024025)(5005006)(10201501046)(3002001); SRVR:SN1NAM02HT120; BCL:0; PCL:0; RULEID:; SRVR:SN1NAM02HT120; X-Forefront-PRVS: 083691450C X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2016 10:31:36.7467 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT120 This patch improves the allocation of registers in the given function. The allocation is optimized for the conditional branches. The temporary register used in the conditional branches to store the comparison results and use of temporary in the conditional branch is optimized. Such temporary registers are allocated with a fixed register r18. Currently such temporaries are allocated with a free registers in the given function. Due to this one of the free register is reserved for the temporaries and given function is left with a few registers. This is unoptimized with respect to microblaze. In Microblaze r18 is marked as fixed and cannot be allocated to pseudos' in the given function. Instead r18 can be used as a temporary for the conditional branches with compare and branch. Use of r18 as a temporary for conditional branches will save one of the free registers to be allocated. The free registers can be used for other pseudos' and hence the better register allocation. The usage of r18 as above reduces the spill and fetch because of the availability of one of the free registers to other pseudos instead of being used for conditional temporaries. The advantage of the above is that the scope of the temporaries is limited to the conditional branches and hence the usage of r18 as temporary for such conditional branches is optimized and preserve the functionality of the function. Regtested for Microblaze target. Performance runs are done with Mibench/EEMBC benchmarks. Following gains are achieved. Benchmarks Gains automotive_qsort1 1.630730524% network_dijkstra 1.527506256% office_stringsearch 1 1.81356288% security_rijndael_d 3.26129357% basefp01_lite 4.465120185% a2time01_lite 1.893862857% cjpeg_lite 3.286496675% djpeg_lite 3.120150612% qos_lite 2.63964381% office_ispell 1.531340405% Code Size improvements: Reduction in number of instructions for Mibench : 12927. Reduction in number of instructions for EEMBC : 212. ChangeLog: 2016-01-29 Ajit Agarwal * config/microblaze/microblaze.c (microblaze_expand_conditional_branch): Use of MB_ABI_ASM_TEMP_REGNUM for temporary conditional branch. (microblaze_expand_conditional_branch_reg): Use of MB_ABI_ASM_TEMP_REGNUM for temporary conditional branch. (microblaze_expand_conditional_branch_sf): Use of MB_ABI_ASM_TEMP_REGNUM for temporary conditional branch. Signed-off-by:Ajit Agarwal ajitkum@xilinx.com. --- gcc/config/microblaze/microblaze.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index baff67a..b4277ad 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -3402,7 +3402,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) rtx cmp_op0 = operands[1]; rtx cmp_op1 = operands[2]; rtx label1 = operands[3]; - rtx comp_reg = gen_reg_rtx (SImode); + rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); rtx condition; gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); @@ -3439,7 +3439,7 @@ microblaze_expand_conditional_branch_reg (enum machine_mode mode, rtx cmp_op0 = operands[1]; rtx cmp_op1 = operands[2]; rtx label1 = operands[3]; - rtx comp_reg = gen_reg_rtx (SImode); + rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); rtx condition; gcc_assert ((GET_CODE (cmp_op0) == REG) @@ -3483,7 +3483,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) rtx condition; rtx cmp_op0 = XEXP (operands[0], 0); rtx cmp_op1 = XEXP (operands[0], 1); - rtx comp_reg = gen_reg_rtx (SImode); + rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);