diff mbox series

[PATCH-1v2,rs6000] Implement optab_isinf for SFDF and IEEE128

Message ID 34db1f19-3e35-4a3b-ae27-3abee76b4b4d@linux.ibm.com
State New
Headers show
Series [PATCH-1v2,rs6000] Implement optab_isinf for SFDF and IEEE128 | expand

Commit Message

HAO CHEN GUI May 20, 2024, 3:28 a.m. UTC 
Hi,
  This patch implemented optab_isinf for SFDF and IEEE128 by test
data class instructions.

  Compared with previous version, the main change is to modify
the dg-options and dg-finals of test cases according to reviewer's
advice.
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/648304.html

  Bootstrapped and tested on powerpc64-linux BE and LE with no
regressions. Is it OK for trunk?

Thanks
Gui Haochen

ChangeLog
rs6000: Implement optab_isinf for SFDF and IEEE128

gcc/
	PR target/97786
	* config/rs6000/vsx.md (isinf<mode>2 for SFDF): New expand.
	(isinf<mode>2 for IEEE128): New expand.

gcc/testsuite/
	PR target/97786
	* gcc.target/powerpc/pr97786-1.c: New test.
	* gcc.target/powerpc/pr97786-2.c: New test.

patch.diff

Comments

Peter Bergner May 22, 2024, 9:58 p.m. UTC | #1 
On 5/19/24 10:28 PM, HAO CHEN GUI wrote:
> +(define_expand "isinf<mode>2"
> +  [(use (match_operand:SI 0 "gpc_reg_operand"))
> +   (use (match_operand:SFDF 1 "gpc_reg_operand"))]
> +  "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
> +{
> +  emit_insn (gen_xststdc<sd>p (operands[0], operands[1], GEN_INT (0x30)));
> +  DONE;
> +})

Is there a reason not to use the vsx_register_operand predicate for op1
which matches the predicate for the operand of the xststdc<sd>p pattern
we're passing op1 to?

Ditto for the other optab patches you've submitted.

Peter
HAO CHEN GUI May 23, 2024, 7:37 a.m. UTC | #2 
Hi Peter,
  Thanks for your comments.

在 2024/5/23 5:58, Peter Bergner 写道:
> Is there a reason not to use the vsx_register_operand predicate for op1
> which matches the predicate for the operand of the xststdc<sd>p pattern
> we're passing op1 to?

No, I will fix them.

Thanks
Gui Haochen
diff mbox series

Patch

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f135fa079bd..fa20fb4df91 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5313,6 +5313,24 @@  (define_expand "xststdc<sd>p"
   operands[4] = CONST0_RTX (SImode);
 })

+(define_expand "isinf<mode>2"
+  [(use (match_operand:SI 0 "gpc_reg_operand"))
+   (use (match_operand:SFDF 1 "gpc_reg_operand"))]
+  "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
+{
+  emit_insn (gen_xststdc<sd>p (operands[0], operands[1], GEN_INT (0x30)));
+  DONE;
+})
+
+(define_expand "isinf<mode>2"
+  [(use (match_operand:SI 0 "gpc_reg_operand"))
+   (use (match_operand:IEEE128 1 "gpc_reg_operand"))]
+  "TARGET_HARD_FLOAT && TARGET_P9_VECTOR"
+{
+  emit_insn (gen_xststdcqp_<mode> (operands[0], operands[1], GEN_INT (0x30)));
+  DONE;
+})
+
 ;; The VSX Scalar Test Negative Quad-Precision
 (define_expand "xststdcnegqp_<mode>"
   [(set (match_dup 2)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-1.c b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c
new file mode 100644
index 00000000000..c1c4f64ee8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97786-1.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+
+int test1 (double x)
+{
+  return __builtin_isinf (x);
+}
+
+int test2 (float x)
+{
+  return __builtin_isinf (x);
+}
+
+int test3 (float x)
+{
+  return __builtin_isinff (x);
+}
+
+/* { dg-final { scan-assembler-not {\mfcmp} } } */
+/* { dg-final { scan-assembler-times {\mxststdcsp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxststdcdp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr97786-2.c b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c
new file mode 100644
index 00000000000..21d90868268
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr97786-2.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target ppc_float128_hw } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -mabi=ieeelongdouble -Wno-psabi" } */
+
+int test1 (long double x)
+{
+  return __builtin_isinf (x);
+}
+
+int test2 (long double x)
+{
+  return __builtin_isinfl (x);
+}
+
+/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */
+/* { dg-final { scan-assembler-times {\mxststdcqp\M} 2 } } */