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[57/57] rs6000: Adjust to late-breaking change

Message ID 331c56de170f60fd0638dbec8654bc1de57a61c8.1619537142.git.wschmidt@linux.ibm.com
State New
Headers show
Series Replace the Power target-specific built-in machinery | expand

Commit Message

Bill Schmidt April 27, 2021, 3:33 p.m. UTC
After this patch set was developed, a small change was made to overload
handling for VEC_INSERT.  Reflecting that into the new support here.

2021-04-27  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	* config/rs6000/rs6000-c.c
	(altivec_resolve_new_overloaded_builtin): Change P8-vector test to
	less-restrictive VSX test in VEC_INSERT handling.
---
 gcc/config/rs6000/rs6000-c.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 1e6fe7699ea..5370dc7608e 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2710,7 +2710,7 @@  altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl,
 	  stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
 	}
 
-      if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
+      if (TARGET_VSX)
 	{
 	  stmt = build_array_ref (loc, stmt, arg2);
 	  stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt,