From patchwork Fri Mar 1 21:55:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 1906911 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=PddBUu/z; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TmhkX3CTWz1yXC for ; Sat, 2 Mar 2024 08:56:34 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B7A7A385840C for ; Fri, 1 Mar 2024 21:56:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by sourceware.org (Postfix) with ESMTPS id C9BC53858C66 for ; Fri, 1 Mar 2024 21:56:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C9BC53858C66 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C9BC53858C66 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::234 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709330167; cv=none; b=PaP8qx2aymurHfv+hwk+r7hWzEjm9kCWhRGttj/sWYMRdgRw23LpXmRmW4BWlATR4KNzG2H4D7Ke9WT2py7cj7IG/MY8BWlK/cK9KNE7YYmk3UTyULz1JzBLo21Tw0IPUWZrqeBYdGmI/nliS1rCIB7quZzSb6stPQBNxPwN7PY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709330167; c=relaxed/simple; bh=xd91cuDhHozjJ2CyDgKRGTL6osRd4Asbyn6Q6STxt8Q=; h=DKIM-Signature:Message-ID:Date:MIME-Version:From:To:Subject; b=T27az8tF3zAbPJLHRm/K8dT+MaRCb25rFUOrGT3lpdubByFb2oQoJ8wS/mXmfxFE0v/7pLz8mQWOiO0s7/WV6uOTt19XIFwbO9iaAHYx7/nYadhgmT0YDw1YOEWjf6sZ+XO/vQCZdkYuV+4Evr3sGjg1D1CkX85gnEW/2TRV/PU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-3bba0ac2e88so2331049b6e.0 for ; Fri, 01 Mar 2024 13:56:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1709330161; x=1709934961; darn=gcc.gnu.org; h=subject:to:from:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=2iiQwoZqgTwmugJE7oXCCO29phT2LGaw7LHIrkZu3MQ=; b=PddBUu/zSxFb1tv7gHrB9EndmvI6U9JJJ5GeYhvuqdcZr/G4Lbm2ogewkDqwq5o+Vv fKDlp2eCmKZFvDlDW4jPDJ8sLSj1TczVokHRGzA8KSFwAV0exOVfnCjdYsRgiZYEu77I sAKYXQxFXutgYUcNTeirF+EhQ7erpAH3nJrTnpItGDpPMEwTy5hUV6iSssqQmYZOXPSo 7M5Ok4b6jqMdLIGYfF8A5N6kVuUfFJVA51cM0KrXB7qUW/eGw8eEkFfyLiLFfSo508eB /NKnkWdsIuNWh3LBPUwXfEbxTf4+JNh+7MiI8A91bFO+OudXH3utiPskjsbpHvJImrbL S5lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709330161; x=1709934961; h=subject:to:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2iiQwoZqgTwmugJE7oXCCO29phT2LGaw7LHIrkZu3MQ=; b=jzXPoxMwlCDJNz+CT/LxOOwf6DlaAy5USmUHj9lXigJyu2u04kr1vEsOtOb6z39An6 gSdnRK9CIg0AFvm5pVT+EUOf9oK5UscnPs38l1wptsMlMkYhPyzmLMvJ3tjp9Ba1JtzL WoLqVPDx6Ds5H/hcDkUQ/Now4avSpLelf40iFqVu4N1B6Iz+hFT4D+Z9wTPIW0pTbR/g R9CzC8hDgfqbQ4O1Qxvngomyf+zymEhdtftLTqAplhL0kjJ6WLlrHt1Du/OhD08g5WkK aNexBmivE8IdVEgP3QIoclHyxnSz/AEnYX/7VnMjfU5WqJx7snUhJXQjDy1SgAkpJ5ZN 6lyw== X-Gm-Message-State: AOJu0YzzAKLRdrGq/pVy3f1s2CRdC/BGYQCc0Ye644QfUXpcVgn50MpD ppfmHyIFdHYUQf5OgASqKQwz+OtG1NOlRdgsB+/6Q5yZikpwIiqhpOxsxNOSQxafPzsS7Q6pwGI n X-Google-Smtp-Source: AGHT+IGy1S3XI4CLTvrkL4Ajy+8HLPi3U8RAlVKNbHlmViU3yBiNjMkNobxNd6kc27jEgrBEuiFQlQ== X-Received: by 2002:a05:6808:21a0:b0:3c1:7ebb:e24f with SMTP id be32-20020a05680821a000b003c17ebbe24fmr3148036oib.16.1709330161050; Fri, 01 Mar 2024 13:56:01 -0800 (PST) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id fu10-20020a0568082a6a00b003c1c7d3399csm690317oib.12.2024.03.01.13.56.00 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 Mar 2024 13:56:00 -0800 (PST) Message-ID: <32f5446d-0b08-4b2f-ad7f-aff42e3987d9@ventanamicro.com> Date: Fri, 1 Mar 2024 14:55:59 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Beta Content-Language: en-US From: Jeff Law To: "gcc-patches@gcc.gnu.org" Subject: [14 regression] Fix insn types in risc-v port X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org So one of the broad goals we've had over the last few months has been to ensure that every insn has a scheduling type and that every insn is associated with an insn reservation in the scheduler. This avoids some amazingly bad behavior in the scheduler. I won't go through the gory details. I was recently analyzing a code quality regression with dhrystone (ugh!) and one of the issues was poor scheduling which lengthened the lifetime of a pseudo and ultimately resulted in needing an additional callee saved register save/restore. This was ultimately tracked down incorrect types on a few patterns. So I did an audit of all the patterns that had types added/changed as part of this effort and found a variety of problems, primarily in the various move patterns and extension patterns. This is a regression relative to gcc-13. Naturally the change in types affects scheduling, which in turn changes the precise code we generate and causes some testsuite fallout. I considered updating the regexps since the change in the resulting output is pretty consistent. But of course the test would still be sensitive to things like load latency. So instead I just turned off the 2nd phase scheduler in the affected tests. Bootstrapped and regression tested on rv64gc-linux-gnu. Pushing to the trunk. jeff gcc * config/riscv/riscv.md (zero_extendqi2_internal): Fix type attribute. (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise. (movdi_32bit, movdi_64bit, movsi_internal): Likewise. (movhi_internal, movqi_internal): Likewise. (movsf_softfloat, movsf_hardfloat): Likewise. (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise. (movdf_softfloat): Likewise. gcc/testsuite * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off second phase scheduler. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1fec13092e2..b16ed97909c 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1836,7 +1836,7 @@ (define_insn "*zero_extendqi2_internal" andi\t%0,%1,0xff lbu\t%0,%1" [(set_attr "move_type" "andi,load") - (set_attr "type" "multi") + (set_attr "type" "arith,load") (set_attr "mode" "")]) ;; @@ -1861,7 +1861,7 @@ (define_insn "*extendsidi2_internal" sext.w\t%0,%1 lw\t%0,%1" [(set_attr "move_type" "move,load") - (set_attr "type" "multi") + (set_attr "type" "move,load") (set_attr "mode" "DI")]) (define_expand "extend2" @@ -1938,7 +1938,7 @@ (define_insn "*movhf_hardfloat" || reg_or_0_operand (operands[1], HFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "HF")]) (define_insn "*movhf_softfloat" @@ -1949,7 +1949,7 @@ (define_insn "*movhf_softfloat" || reg_or_0_operand (operands[1], HFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,move,load,store,mtc,mfc") - (set_attr "type" "fmove") + (set_attr "type" "fmove,move,load,store,mtc,mfc") (set_attr "mode" "HF")]) (define_insn "*movhf_softfloat_boxing" @@ -2182,7 +2182,7 @@ (define_insn "*movdi_32bit" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") (set_attr "mode" "DI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,move,fpload,move,fmove,fpstore,move") (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) (define_insn "*movdi_64bit" @@ -2194,7 +2194,7 @@ (define_insn "*movdi_64bit" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") (set_attr "mode" "DI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fmove,fpstore,move") (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) ;; 32-bit Integer moves @@ -2217,7 +2217,7 @@ (define_insn "*movsi_internal" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") (set_attr "mode" "SI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fpstore,move") (set_attr "ext" "base,base,base,base,f,f,f,f,vector")]) ;; 16-bit Integer moves @@ -2244,7 +2244,7 @@ (define_insn "*movhi_internal" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") (set_attr "mode" "HI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,mfc,move") (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; HImode constant generation; see riscv_move_integer for details. @@ -2288,7 +2288,7 @@ (define_insn "*movqi_internal" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") (set_attr "mode" "QI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,mfc,move") (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; 32-bit floating point moves @@ -2310,7 +2310,7 @@ (define_insn "*movsf_hardfloat" || reg_or_0_operand (operands[1], SFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "SF")]) (define_insn "*movsf_softfloat" @@ -2321,7 +2321,7 @@ (define_insn "*movsf_softfloat" || reg_or_0_operand (operands[1], SFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "move,load,store") (set_attr "mode" "SF")]) ;; 64-bit floating point moves @@ -2346,7 +2346,7 @@ (define_insn "*movdf_hardfloat_rv32" || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "DF")]) (define_insn "*movdf_hardfloat_rv64" @@ -2357,7 +2357,7 @@ (define_insn "*movdf_hardfloat_rv64" || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "DF")]) (define_insn "*movdf_softfloat" @@ -2368,7 +2368,7 @@ (define_insn "*movdf_softfloat" || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fpload,fpstore") (set_attr "mode" "DF")]) (define_insn "movsidf2_low_rv32" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c index 28b8a82096a..60c838eb21d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c index d45fb4c1f2f..b9922a64332 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c index 1885004fda4..989d45de254 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c index 3a4ed22614c..b8bb2932de8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c index e3f3b397f3f..f0357d30aec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c index 4c876ac3b86..edf6539b0f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c index 5542d4878ff..e001a73de52 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h"