diff mbox series

[v2,3/3] RISC-V: Add stub support for existing extensions (unprivileged)

Message ID 3091a5d106d2d8256723c6a74f08f8607c9f019f.1691993380.git.research_trasio@irq.a4lg.com
State New
Headers show
Series RISC-V: Add stub support for existing extensions | expand

Commit Message

Tsukasa OI Aug. 14, 2023, 6:09 a.m. UTC
From: Tsukasa OI <research_trasio@irq.a4lg.com>

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

This commit adds stub supported standard unprivileged extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c except not yet
merged 'Zce', 'Zcmp' and 'Zcmt' support).

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc
	(riscv_implied_info): Add implications from unprivileged extensions.
	(riscv_ext_version_table): Add stub support for all unprivileged
	extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/predef-31.c: New test for a stub unprivileged
	extension 'Zcb' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc    | 24 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 ++++++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c

Comments

Jeff Law Aug. 29, 2023, 1:42 a.m. UTC | #1
On 8/14/23 00:09, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
> extensions") changed how do we handle unknown extensions, we have no
> guarantee that we can share the same architectural string with Binutils
> (specifically, the assembler).
> 
> To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
> support almost all extensions that Binutils support, even if the GCC does
> not touch a thing.
> 
> This commit adds stub supported standard unprivileged extensions to
> riscv_ext_version_table and its implications to riscv_implied_info
> (all information is copied from Binutils' bfd/elfxx-riscv.c except not yet
> merged 'Zce', 'Zcmp' and 'Zcmt' support).
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc
> 	(riscv_implied_info): Add implications from unprivileged extensions.
> 	(riscv_ext_version_table): Add stub support for all unprivileged
> 	extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/predef-31.c: New test for a stub unprivileged
> 	extension 'Zcb' with some implications.
This series (most likely patch 3/3) seems to break arch-24.c and arch-25.c.

Please fix and post a V3.

Jeff
Tsukasa OI Aug. 29, 2023, 3:14 a.m. UTC | #2
On 2023/08/29 10:42, Jeff Law wrote:
> 
> 
> On 8/14/23 00:09, Tsukasa OI wrote:
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
>> extensions") changed how do we handle unknown extensions, we have no
>> guarantee that we can share the same architectural string with Binutils
>> (specifically, the assembler).
>>
>> To avoid compilation errors on shared Assembler-C/C++ projects, GCC
>> should
>> support almost all extensions that Binutils support, even if the GCC does
>> not touch a thing.
>>
>> This commit adds stub supported standard unprivileged extensions to
>> riscv_ext_version_table and its implications to riscv_implied_info
>> (all information is copied from Binutils' bfd/elfxx-riscv.c except not
>> yet
>> merged 'Zce', 'Zcmp' and 'Zcmt' support).
>>
>> gcc/ChangeLog:
>>
>>     * common/config/riscv/riscv-common.cc
>>     (riscv_implied_info): Add implications from unprivileged extensions.
>>     (riscv_ext_version_table): Add stub support for all unprivileged
>>     extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/predef-31.c: New test for a stub unprivileged
>>     extension 'Zcb' with some implications.
> This series (most likely patch 3/3) seems to break arch-24.c and arch-25.c.
> 
> Please fix and post a V3.
> 
> Jeff
> 

I think it was a hidden merge failure with partial Zc* extensions
support by Jiawei (and I already fixed it in the internal version).
I'll re-review it and submit as v3 if it's okay.

I don't recall exact test cases that failed (when I tested) but looking
at arch-24.c and arch-25.c you pointed out, they have a minor issue
(independent with this patch set).  I'll submit a minor fix for those
files later.

Thanks,
Tsukasa
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 0c351105e015..27e9072899bf 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -121,6 +121,20 @@  static const riscv_implied_info_t riscv_implied_info[] =
   {"zvksg", "zvks"},
   {"zvksg", "zvkg"},
 
+  {"zcb", "zca"},
+  {"zcd", "zca"},
+  {"zcd", "d"},
+  {"zcf", "zca"},
+  {"zcf", "f"},
+  {"zce", "zca"},
+  {"zce", "zcb"},
+  {"zce", "zcmp"},
+  {"zce", "zcmt"},
+  {"zcmp", "zca"},
+  {"zcmt", "zca"},
+  {"zcmt", "zcicsr"},
+
+  {"zfa", "f"},
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   {"zvfhmin", "zve32f"},
@@ -197,6 +211,14 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
 
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zca",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zce",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcf",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -219,6 +241,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
 
   {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -265,6 +288,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfa",       ISA_SPEC_CLASS_NONE, 0, 1},
   {"zfh",       ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-31.c b/gcc/testsuite/gcc.target/riscv/predef-31.c
new file mode 100644
index 000000000000..4ea11442f995
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-31.c
@@ -0,0 +1,31 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcb -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zca)
+#error "__riscv_zca"
+#endif
+
+#if !defined(__riscv_zcb)
+#error "__riscv_zcb"
+#endif
+
+  return 0;
+}